NTD50N03R
Power MOSFET
25 V, 45 A, Single N−Channel, DPAK
Features
•
•
•
•
•
Planar Technology
Low R
DS(on)
to Minimize Conduction Losses
Low Capacitance to Minimize Driver Losses
Optimized Gate Charge to Minimize Switching Losses
Pb−Free Packages are Available
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V
(BR)DSS
25 V
R
DS(on)
TYP
12.5 mW @ 10 V
19 mW @ 4.5 V
N−Channel
D
I
D
MAX
45 A
Applications
•
VCORE DC−DC Buck Converter Applications
•
Optimized for High Side Switching
MAXIMUM RATINGS
(T
J
= 25°C unless otherwise noted)
Parameter
Drain−to−Source Voltage
Gate−to−Source Voltage
Continuous Drain
Current (R
qJA
)
(Note 1)
Power Dissipation
(R
qJA
) (Note 1)
Continuous Drain
Current (R
qJA
)
(Note 2)
Power Dissipation
(R
qJA
) (Note 2)
Continuous Drain
Current (R
qJC
)
(Note 1)
Power Dissipation
(R
qJC
) (Note 1)
Pulsed Drain Current
Current Limited by
Package
T
A
= 25°C
T
A
= 85°C
T
A
= 25°C
T
A
= 25°C
Steady
State
T
A
= 85°C
T
A
= 25°C
T
C
= 25°C
T
C
= 85°C
T
C
= 25°C
T
A
= 25°C,
t
p
= 10
ms
T
A
= 25°C
P
D
I
DM
I
DmaxPkg
T
J
, T
stg
I
S
dv/dt
E
AS
P
D
I
D
P
D
I
D
Symbol
V
DSS
V
GS
I
D
Value
25
"20
9.2
7.2
2.1
7.8
6.0
1.5
45
35
50
180
45
−55 to
175
45
8.0
20
W
A
A
°C
A
V/ns
mJ
W
A
W
Unit
V
V
A
G
S
4
4
4
A
1 2
2 3
3
CASE 369AA
CASE 369D
CASE 369AC
DPAK
DPAK
3 IPAK
(Surface Mount) (Straight Lead) (Straight Lead)
STYLE 2
STYLE 2
2
3
1
1
MARKING DIAGRAMS
& PIN ASSIGNMENTS
4
Drain
YWW
T50
N03RG
3
Source
1
Gate
2
Drain
3
Source
= Year
= Work Week
= Device Code
= Pb−Free Package
Publication Order Number:
NTD50N03R/D
4
Drain
YWW
T50
N03RG
1
Gate
2
Drain
Y
WW
T50N03R
G
Operating Junction and Storage
Temperature
Source Current (Body Diode)
Drain−to−Source (dv/dt)
Single Pulse Drain−to−Source Avalanche
Energy (T
J
= 25°C, V
DD
= 50 V, V
GS
= 10 V,
I
L
= 6.32 A
pk
, L = 1.0 mH, R
G
= 25
W)
Lead Temperature for Soldering Purposes
(1/8″ from case for 10 s)
T
L
260
°C
Stresses exceeding Maximum Ratings may damage the device. Maximum
Ratings are stress ratings only. Functional operation above the Recommended
Operating Conditions is not implied. Extended exposure to stresses above the
Recommended Operating Conditions may affect device reliability.
1. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu.
2. Surface−mounted on FR4 board using the minimum recommended pad size.
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 6 of this data sheet.
©
Semiconductor Components Industries, LLC, 2007
1
March, 2007 − Rev. 4
NTD50N03R
THERMAL RESISTANCE MAXIMUM RATINGS
Parameter
Junction−to−Case (Drain)
Junction−to−Ambient − Steady State (Note 3)
Junction−to−Ambient − Steady State (Note 4)
Symbol
R
qJC
R
qJA
R
qJA
Value
3.0
71.4
100
Unit
°C/W
ELECTRICAL CHARACTERISTICS
(T
J
= 25°C unless otherwise noted)
Parameter
OFF CHARACTERISTICS
Drain−to−Source Breakdown Voltage
Drain−to−Source Breakdown Voltage
Temperature Coefficient
Zero Gate Voltage Drain Current
V
(BR)DSS
V
(BR)DSS
/T
J
I
DSS
V
GS
= 0 V,
V
DS
= 20 V
T
J
= 25°C
T
J
= 125°C
V
GS
= 0 V, I
D
= 250
mA
25
−16
1.5
10
"100
nA
V
mV/°C
mA
Symbol
Test Condition
Min
Typ
Max
Unit
Gate−to−Source Leakage Current
ON CHARACTERISTICS
(Note 5)
Gate Threshold Voltage
Negative Threshold Temperature Coefficient
Drain−to−Source On Resistance
I
GSS
V
DS
= 0 V, V
GS
=
"20
V
V
GS
= V
DS
, I
D
= 250
mA
V
GS(TH)
V
GS(TH)
/T
J
R
DS(on)
1.0
1.7
−5.0
2.0
V
mV/°C
mW
V
GS
= 11.5 V
V
GS
= 10 V
V
GS
= 4.5 V
I
D
= 30 A
I
D
= 15 A
I
D
= 30 A
I
D
= 30 A
I
D
= 15 A
12
11.7
12.5
21
19
15
23
14
Forward Transconductance
g
FS
V
DS
= 15 V, I
D
= 15 A
S
CHARGES, CAPACITANCES AND GATE RESISTANCE
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
Total Gate Charge
Threshold Gate Charge
Gate−to−Source Charge
Gate−to−Drain Charge
C
iss
C
oss
C
rss
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
Q
G(TOT)
Q
G(TH)
Q
GS
Q
GD
V
GS
= 11.5 V, V
DS
= 15 V,
I
D
= 30 A
V
GS
= 4.5 V, V
DS
= 15 V,
I
D
= 30 A
V
GS
= 0 V, f = 1.0 MHz,
V
DS
= 12 V
610
300
125
6.0
0.9
1.9
3.7
15
1.0
1.9
3.9
nC
10
nC
750
pF
3. Surface−mounted on FR4 board using 1 sq in pad, 1 oz Cu.
4. Surface−mounted on FR4 board using the minimum recommended pad size.
5. Pulse Test: Pulse Width
≤
300
ms,
Duty Cycle
≤
2%.
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NTD50N03R
ELECTRICAL CHARACTERISTICS
(continued) (T
J
= 25°C unless otherwise noted)
Parameter
SWITCHING CHARACTERISTICS
(Note 6)
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
Turn−On Delay Time
Rise Time
Turn−Off Delay Time
Fall Time
DRAIN−SOURCE DIODE CHARACTERISTICS
Forward Diode Voltage
V
SD
V
GS
= 0 V,
I
S
= 30 A
T
J
= 25°C
T
J
= 125°C
0.85
0.71
24
V
GS
= 0 V, dI
S
/dt = 100 A/ms,
I
S
= 30 A
14
10.5
14
nC
ns
1.1
V
t
d(on)
t
r
t
d(off)
t
f
t
d(on)
t
r
t
d(off)
t
f
V
GS
= 11.5 V, V
DS
= 15 V,
I
D
= 30 A, R
G
= 3.0
W
V
GS
= 4.5 V, V
DS
= 15 V,
I
D
= 30 A, R
G
= 3.0
W
8.2
9.6
11.2
6.8
5.0
84
15
4.0
ns
ns
Symbol
Test Condition
Min
Typ
Max
Unit
Reverse Recovery Time
Charge Time
Discharge Time
Reverse Recovery Charge
PACKAGE PARASITIC VALUES
Source Inductance
Drain Inductance
Gate Inductance
Gate Resistance
t
RR
t
a
t
b
Q
RR
L
S
L
D
L
G
R
G
Ta = 25C
2.49
0.02
3.46
3.75
W
nH
6. Switching characteristics are independent of operating junction temperatures.
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3
NTD50N03R
100
I
D
, DRAIN CURRENT (AMPS)
10 V
100
8V
7V
6V
I
D
, DRAIN CURRENT (AMPS)
5.5 V
5V
4.5 V
4V
40
3.5 V
V
GS
= 2.6 V
2.8 V
3V
V
DS
≥
10 V
80
T
J
= −55°C
T
J
= 25°C
T
J
= 125°C
80
60
60
40
20
0
0
1
2
3
20
0
4
5
6
7
8
9
10
0
1
2
3
4
5
6
7
8
9
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
Figure 1. On−Region Characteristics
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE (W)
Figure 2. Transfer Characteristics
0.065
0.055
0.045
I
D
= 15 A
T
J
= 25°C
0.030
T
J
= 25°C
0.025
V
GS
= 4.5 V
0.020
0.015
0.010
0.005
0
10
V
GS
= 10 V
0.035
0.025
0.015
0.005
2
3
4
5
6
7
8
9
10
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
20
30
40
50
I
D
, DRAIN CURRENT (AMPS)
Figure 3. On−Resistance versus
Gate−to−Source Voltage
R
DS(on)
, DRAIN−TO−SOURCE RESISTANCE
(NORMALIZED)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
−50 −25
100
0
25
50
75
100
125
150
175
I
D
= 10 A
V
GS
= 10 V
I
DSS
, LEAKAGE (nA)
10,000
Figure 4. On−Resistance versus Drain Current
and Gate Voltage
V
GS
= 0 V
T
J
= 150°C
1000
T
J
= 125°C
0
5
10
15
20
25
T
J
, JUNCTION TEMPERATURE (°C)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 5. On−Resistance Variation with
Temperature
Figure 6. Drain−to−Source Leakage Current
versus Voltage
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NTD50N03R
V
GS
, GATE−TO−SOURCE VOLTAGE (VOLTS)
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
1000
V
DS
= 0 V V
GS
= 0 V
C, CAPACITANCE (pF)
800
C
iss
C
rss
600
T
J
= 25°C
16
16
12
V
DS
8
Q
GS
4
Q
GD
Q
T
V
GS
12
C
iss
8
400
C
oss
200
0
10
5
V
GS
0 V
DS
5
10
15
20
GATE−TO−SOURCE OR DRAIN−TO−SOURCE VOLTAGE
(VOLTS)
C
rss
4
I
D
= 30 A
T
J
= 25°C
0
0
2
4
6
8
10
12
14
Q
g
, TOTAL GATE CHARGE (nC)
0
16
Figure 7. Capacitance Variation
Figure 8. Gate−to−Source and
Drain−to−Source Voltage versus Total Charge
20
I
S
, SOURCE CURRENT (AMPS)
100
V
DS
= 10 V
I
D
= 10 A
V
GS
= 10 V
t, TIME (ns)
t
r
t
d(off)
10
t
d(on)
t
f
18
16
14
12
10
8
6
4
2
0
0
V
GS
= 0 V
T
J
= 25°C
1
1
10
R
G
, GATE RESISTANCE (W)
100
0.2
0.4
0.6
0.8
1.0
V
SD
, SOURCE−TO−DRAIN VOLTAGE (VOLTS)
Figure 9. Resistive Switching Time Variation
versus Gate Resistance
Figure 10. Diode Forward Voltage versus
Current
1000
I D, DRAIN CURRENT (AMPS)
SINGLE PULSE
V
GS
= 20 V
T
C
= 25°C
10
ms
100
100
ms
10
R
DS(on)
LIMIT
THERMAL LIMIT
PACKAGE LIMIT
0.1
1 ms
10 ms
dc
100
1
1
10
V
DS
, DRAIN−TO−SOURCE VOLTAGE (VOLTS)
Figure 11. Maximum Rated Forward Biased
Safe Operating Area
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