INTEGRATED CIRCUITS
74ALVT16373
2.5V/3.3V 16-bit transparent
D-type latch (3-State)
Product specification
Supersedes data of 1998 Feb 13
IC23 Data Handbook
1999 Oct 18
Philips
Semiconductors
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit transparent D-type latch (3-State)
74ALVT16373
FEATURES
•
16-bit transparent latch
•
5V I/O compatibile
•
3-State buffers
•
Output capability: +64mA/-32mA
•
TTL input and output switching levels
•
Input and output interface capability to systems at 5V supply
•
Bus-hold data inputs eliminate the need for external pull-up
resistors to hold unused inputs
DESCRIPTION
The 74ALVT16373 is a high-performance BiCMOS product
designed for V
CC
operation at 2.5V or 3.3V with I/O compatibility up
to 5V.
This device is a 16-bit transparent D-type latch with non-inverting
3-State bus compatible outputs. The device can be used as two
8-bit latches or one 16-bit latch. When latch enable (LE) input is
High, the Q outputs follow the data (D) inputs. When latch enable is
taken Low, the Q outputs are latched at the levels of the D inputs
one setup time prior to the High-to-Low transition.
•
Live insertion/extraction permitted
•
Power-up reset
•
Power-up 3-State
•
No bus current loading when output is tied to 5V bus
•
Latch-up protection exceeds 500mA per JEDEC Std 17
•
ESD protection exceeds 2000V per MIL STD 883 Method 3015
and 200V per Machine Model
QUICK REFERENCE DATA
SYMBOL
t
PLH
t
PHL
C
IN
C
OUT
I
CCZ
PARAMETER
Propagation delay
nDx to nQx
Input capacitance
Output capacitance
Total supply current
C
L
= 50pF
V
I
= 0V or V
CC
Outputs disabled; V
O
= 0V or 3.0V
Outputs disabled
CONDITIONS
T
amb
= 25°C
TYPICAL
UNIT
2.5V
2.0
2.4
3
9
40
3.3V
1.6
1.8
3
9
70
ns
pF
pF
µA
ORDERING INFORMATION
PACKAGES
48-Pin Plastic SSOP Type III
48-Pin Plastic TSSOP Type II
TEMPERATURE RANGE
–40°C to +85°C
–40°C to +85°C
OUTSIDE NORTH AMERICA
74ALVT16373 DL
74ALVT16373 DGG
NORTH AMERICA
AV16373 DL
AV16373 DGG
DWG NUMBER
SOT370-1
SOT362-1
1999 Oct 18
2
853-1842 22536
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit transparent D-type latch (3-State)
74ALVT16373
LOGIC SYMBOL
47
46
44
43
41
40
38
37
LOGIC SYMBOL (IEEE/IEC)
1OE
1LE
1
48
24
25
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
4D
2
∇
1EN
C3
2EN
C4
1
∇
2
3
5
6
8
9
11
12
13
14
16
17
19
20
22
23
1D0 1D1 1D2 1D3 1D4 1D5 1D6 1D7
48
1
1LE
1OE
1Q0 1Q1 1Q2 1Q3 1Q4 1Q5 1Q6 1Q7
2OE
2LE
1D1
1D2
1D3
3D
1Q1
1Q2
1Q3
1Q4
1Q5
1Q6
1Q7
1Q8
2Q1
2Q2
2Q3
2Q4
2Q5
2Q6
2Q7
2Q8
2
36
3
35
5
33
6
32
8
30
9
29
11
27
12
26
1D4
1D5
1D6
1D7
2D0 2D21 2D2 2D3 2D4 2D5 2D6 2D7
25
24
2LE
2OE
2Q0 2Q1 2Q2 2Q3 2Q4 2Q5 2Q6 2Q7
1D8
2D1
2D2
2D3
2D4
13
14
16
17
19
20
22
23
2D5
2D6
2D7
SA00044
PIN DESCRIPTION
PIN NUMBER
47, 46, 44, 43, 41, 40, 38, 37,
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12, 13,
14, 16, 17, 19, 20, 22, 23
1, 24
SYMBOL
1D0 – 1D7
2D0 – 2D7
1Q0 – 1Q7
2Q0 – 2Q7
1OE, 2OE
FUNCTION
Data inputs
Data outputs
Output enable
inputs
(active-Low)
Enable inputs
(active-High)
Ground (0V)
Positive
supply voltage
2D8
SW00010
PIN CONFIGURATION
1OE
1Q0
1Q1
GND
1Q2
1Q3
V
CC
1Q4
1Q5
GND
1Q6
1Q7
2Q0
2Q1
GND
2Q2
2Q3
V
CC
2Q4
2Q5
GND
2Q6
2Q7
2OE
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
1LE
1D0
1D1
GND
1D2
1D3
V
CC
1D4
1D5
GND
1D6
1D7
2D0
2D1
GND
2D2
2D3
V
CC
2D4
2D5
GND
2D6
2D7
2LE
48, 25
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
1LE, 2LE
GND
V
CC
SA00043
1999 Oct 18
3
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit transparent D-type latch (3-State)
74ALVT16373
LOGIC DIAGRAM
nD0
nD1
nD2
nD3
nD4
nD5
nD6
nD7
D
D
D
D
D
D
D
D
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
E
Q
nLE
nOE
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
SA00046
FUNCTION TABLE
INPUTS
nOE
L
L
L
L
L
H
H
H =
h =
L =
l =
NC=
X =
Z =
↓
=
nLE
H
H
↓
↓
L
L
H
nDx
L
H
l
h
X
X
nDx
INTERNAL
REGISTER
L
H
L
H
NC
NC
nDx
OUTPUTS
nQ0 – nQ7
L
H
L
H
NC
Z
Z
OPERATING MODE
Enable and read register
Latch and read register
Hold
Disable outputs
High voltage level
High voltage level one set-up time prior to the High-to-Low E transition
Low voltage level
Low voltage level one set-up time prior to the High-to-Low E transition
No change
Don’t care
High impedance “off ” state
High-to-Low E transition
1999 Oct 18
4
Philips Semiconductors
Product specification
2.5V/3.3V 16-bit transparent D-type latch (3-State)
74ALVT16373
ABSOLUTE MAXIMUM RATINGS
1, 2
SYMBOL
V
CC
I
IK
V
I
I
OK
V
OUT
I
O
OUT
T
stg
PARAMETER
DC supply voltage
DC input diode current
DC input voltage
3
DC output diode current
DC output voltage
3
DC output current
Output in High state
Storage temperature range
–64
–65 to +150
°C
V
O
< 0
Output in Off or High state
Output in Low state
V
I
< 0
CONDITIONS
RATING
–0.5 to +4.6
–50
–0.5 to +7.0
–50
–0.5 to +7.0
128
mA
UNIT
V
mA
V
mA
V
NOTES:
1. Stresses beyond those listed may cause permanent damage to the device. These are stress ratings only and functional operation of the
device at these or any other conditions beyond those indicated under “recommended operating conditions” is not implied. Exposure to
absolute-maximum-rated conditions for extended periods may affect device reliability.
2. The performance capability of a high-performance integrated circuit in conjunction with its thermal environment can create junction
temperatures which are detrimental to reliability. The maximum junction temperature of this integrated circuit should not exceed 150°C.
3. The input and output negative voltage ratings may be exceeded if the input and output clamp current ratings are observed.
RECOMMENDED OPERATING CONDITIONS
SYMBOL
V
CC
V
I
V
IH
V
IL
I
OH
I
OL
∆t/∆v
T
amb
DC supply voltage
Input voltage
High-level input voltage
Input voltage
High-level output current
Low-level output current
Low-level output current; current duty cycle
≤
50%; f
≥
1kHz
Input transition rise or fall rate; Outputs enabled
Operating free-air temperature range
–40
PARAMETER
2.5V RANGE LIMITS
MIN
2.3
0
1.7
0.7
–8
8
24
10
+85
–40
MAX
2.7
5.5
3.3V RANGE LIMITS
MIN
3.0
0
2.0
0.8
–32
32
64
10
+85
MAX
3.6
5.5
UNIT
V
V
V
V
mA
mA
ns/V
°C
1999 Oct 18
5
FPGA/CPLD
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