CY7C4255V
CY7C4275V
CY7C4285V
8 K/32 K/64 K × 18 Low Voltage
Deep Sync FIFOs
8 K/32 K/64 K × 18 Low Voltage Deep Sync FIFOs
Features
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Functional Description
The CY7C4255/75/85V are high speed, low power, first-in
first-out (FIFO) memories with clocked read and write interfaces.
All are 18 bits wide and are pin and functionally compatible to the
CY7C42X5V Synchronous FIFO family. The CY7C4255/75/85V
can be cascaded to increase FIFO depth. Programmable
features include Almost Full/Almost Empty flags. These FIFOs
provide solutions for a wide variety of data buffering needs,
including high speed data acquisition, multiprocessor interfaces,
and communications buffering.
These FIFOs have 18-bit input and output ports that are
controlled by separate clock and enable signals. The input port
is controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is
continually written into the FIFO on each cycle. The output port
is controlled in a similar manner by a free-running read clock
(RCLK) and a read enable pin (REN). In addition, the
CY7C4255/75/85V have an output enable pin (OE). The read
and write clocks may be tied together for single-clock operation
or the two clocks may be run independently for asynchronous
read or write applications. Clock frequencies up to 67 MHz are
achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI, RXI),
cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of
the next device, and the WXO and RXO pins of the last device
must be connected to the WXI and RXI pins of the first device.
The FL pin of the first device is tied to VSS and the FL pin of all
the remaining devices must be tied to VCC.
For a complete list of related documentation,
click here.
3.3 V operation for low power consumption and easy integration
into low voltage systems
High speed, low power, first-in first-out (FIFO) memories
8 K × 18 (CY7C4255V)
32 K × 18 (CY7C4275V)
64 K × 18 (CY7C4285V)
0.35 micron CMOS for optimum speed and power
High speed 100 MHz operation (10 ns read/write cycle times)
Low power
❐
I
CC
= 30 mA
❐
I
SB
= 4 mA
Fully asynchronous and simultaneous read and write operation
Empty, Full, Half Full, and programmable Almost Empty and
Almost Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
64-pin 10 × 10 STQFP
Pin compatible density upgrade to CY7C42X5V-ASC families
Pin compatible 3.3 V solutions for CY7C4255/75/85V
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Selection Guide
Parameter
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Setup (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply Current (I
CC1
) (mA)
Commercial
Industrial
7C4255/75/85V-10
100
8
10
3.5
0
8
30
7C4255/75/85V-15
66.7
10
15
4
0
10
30
35
Cypress Semiconductor Corporation
Document Number: 38-06012 Rev. *F
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised November 20, 2014
CY7C4255V
CY7C4275V
CY7C4285V
Parameter
Density
Package
8 K × 18
CY7C4255V
32 K × 18
64-pin 10 × 10 TQFP
CY7C4275V
64 K × 18
64-pin 10 × 10 TQFP
CY7C4285V
64-pin 10 × 10 TQFP
Logic Block Diagram
D
0 – 17
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
High
Density
Dual-Port
RAM Array
8 K x 18
32 K x 18
64 K x 18
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE-ST ATE
OUTPUT REGISTER
Q
0 – 17
OE
READ
CONTROL
RCLK
REN
Document Number: 38-06012 Rev. *F
Page 2 of 25
CY7C4255V
CY7C4275V
CY7C4285V
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Functional Description ..................................................... 6
Architecture ...................................................................... 6
Resetting the FIFO ............................................................ 6
FIFO Operation ................................................................. 6
Programming .................................................................... 6
Flag Operation .................................................................. 6
Full Flag ....................................................................... 6
Empty Flag .................................................................. 6
Programmable Almost Empty/Almost Full Flag ........... 7
Retransmit ......................................................................... 7
Width Expansion Configuration ...................................... 7
Depth Expansion Configuration
(with Programmable Flags) ............................................. 8
Maximum Ratings ........................................................... 10
Operating Range ............................................................. 10
Electrical Characteristics ............................................... 10
Capacitance .................................................................... 11
AC Test Loads and Waveforms ..................................... 11
Switching Characteristics .............................................. 12
Switching Waveforms .................................................... 13
Ordering Information ...................................................... 21
Ordering Code Definitions ......................................... 21
Package Diagram ............................................................ 22
Acronyms ........................................................................ 23
Document Conventions ................................................. 23
Units of Measure ....................................................... 23
Document History Page ................................................. 24
Sales, Solutions, and Legal Information ...................... 25
Worldwide Sales and Design Support ....................... 25
Products .................................................................... 25
PSoC® Solutions ...................................................... 25
Cypress Developer Community ................................. 25
Technical Support ..................................................... 25
Document Number: 38-06012 Rev. *F
Page 3 of 25
CY7C4255V
CY7C4275V
CY7C4285V
Pin Configurations
Figure 1. 64-pin STQFP pinout
REN
LD
OE
RS
V
CC
GND
EF
Q
17
Q
16
GND
Q
15
V
CC
/SMODE
Top View
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
D
16
D
17
GND
RCLK
FL/RT
WCLK
WEN
WXI
V
CC
PAF
RXI
FF
WXO/HF
RXO
PAE
Q
0
Q
1
GND
Q
2
Document Number: 38-06012 Rev. *F
Q
3
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
CY7C4255V
CY7C4275V
CY7C4285V
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
Page 4 of 25
CY7C4255V
CY7C4275V
CY7C4285V
Pin Definitions
CY7C4255/75/85V 64-pin STQFP
Signal Name
D
0–17
Q
0–17
WEN
REN
WCLK
RCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
Read Clock
I/O
I
O
I
I
I
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not Full.
When LD is asserted, WCLK writes data into the programmable flag-offset register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-offset
register.
Dual Mode Pin:
Single device or width expansion – Half Full status flag
Cascaded – Write Expansion Out signal, connected to WXI of next device
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost empty offset value
programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied to V
CC
.
It is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to V
CC
.
It is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0–17
(Q
0–17
) are written (read) into (from) the
programmable-flag-offset register.
Dual Mode Pin:
Cascaded – The first device in the daisy chain has FL tied to V
SS
; all other devices have
FL tied to V
CC
. In standard mode or width expansion, FL is tied to V
SS
on all devices.
Not Cascaded – Tied to V
SS
. Retransmit function is also available in standalone mode
by strobing RT.
Cascaded – Connected to WXO of previous device
Not Cascaded – Tied to V
SS
Cascaded – Connected to RXO of previous device
Not Cascaded – Tied to V
SS
Cascaded – Connected to RXI of next device
Resets device to empty condition. A reset is required before an initial read or write
operation after power up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are connected. If
OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual Mode Pin:
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
Synchronous Almost Empty/Almost Full flags – tied to V
SS
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
Function
WXO/HF
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
O
EF
FF
PAE
O
O
O
PAF
O
LD
FL/RT
I
I
WXI
RXI
RXO
RS
OE
V
CC
/SMODE
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
I
I
O
I
I
I
Document Number: 38-06012 Rev. *F
Page 5 of 25
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