SAA7104E; SAA7105E
Digital video encoder
Rev. 02 — 23 December 2005
Product data sheet
1. General description
The SAA7104E; SAA7105E is an advanced next-generation video encoder which
converts PC graphics data at maximum 1280
×
1024 resolution (optionally 1920
×
1080
interlaced) to PAL (50 Hz) or NTSC (60 Hz) video signals. A programmable scaler and
anti-flicker filter (maximum 5 lines) ensures properly sized and flicker-free TV display as
CVBS or S-video output.
Alternatively, the three Digital-to-Analog Converters (DACs) can output RGB signals
together with a TTL composite sync to feed SCART connectors.
When the scaler/interlacer is bypassed, a second VGA monitor can be connected to the
RGB outputs and separate H and V-syncs as well, thereby serving as an auxiliary monitor
at maximum 1280
×
1024 resolution/60 Hz (PIXCLK < 85 MHz). Alternatively this port
can provide Y, P
B
and P
R
signals for HDTV monitors.
The device includes a sync/clock generator and on-chip DACs.
All inputs intended to interface to the host graphics controller are designed for low-voltage
signals between down to 1.1 V and up to 3.6 V.
2. Features
s
Digital PAL/NTSC encoder with integrated high quality scaler and anti-flicker filter for
TV output from a PC
s
Supports Intel Digital Video Out (DVO) low voltage interfacing to graphics controller
s
27 MHz crystal-stable subcarrier generation
s
Maximum graphics pixel clock 85 MHz at double edged clocking, synthesized on-chip
or from external source
s
Programmable assignment of clock edge to bytes (in double edged mode)
s
Synthesizable pixel clock (PIXCLK) with minimized output jitter, can be used as
reference clock for the VGC, as well
s
PIXCLK output and bi-phase PIXCLK input (VGC clock loop-through possible)
s
Hot-plug detection through dedicated interrupt pin
s
Supported VGA resolutions for PAL or NTSC legacy video output up to 1280
×
1024
graphics data at 60 Hz or 50 Hz frame rate
s
Supported VGA resolutions for HDTV output up to 1920
×
1080 interlaced graphics
data at 60 Hz or 50 Hz frame rate
s
Three Digital-to-Analog Converters (DACs) at 27 MHz sample rate for CVBS (BLUE,
C
B
), VBS (GREEN, CVBS) and C (RED, C
R
) (signals in parenthesis are optional); all at
10-bit resolution
s
Non-Interlaced (NI) C
B
-Y-C
R
or RGB input at maximum 4 : 4 : 4 sampling
Philips Semiconductors
SAA7104E; SAA7105E
Digital video encoder
s
Downscaling and upscaling from 50 % to 400 %
s
Optional interlaced C
B
-Y-C
R
input of Digital Versatile Disc (DVD) signals
s
Optional non-interlaced RGB output to drive second VGA monitor (bypass mode with
maximum 85 MHz)
s
3 bytes
×
256 bytes RGB Look-Up Table (LUT)
s
Support for hardware cursor
s
HDTV up to 1920
×
1080 interlaced and 1280
×
720 progressive, including 3-level
sync pulses
s
Programmable border color of underscan area
s
Programmable 5 line anti-flicker filter
s
On-chip 27 MHz crystal oscillator (3rd-harmonic or fundamental 27 MHz crystal)
s
Fast I
2
C-bus control port (400 kHz)
s
Encoder can be master or slave
s
Adjustable output levels for the DACs
s
Programmable horizontal and vertical input synchronization phase
s
Programmable horizontal sync output phase
s
Internal Color Bar Generator (CBG)
s
Optional support of various Vertical Blanking Interval (VBI) data insertion
s
Macrovision Pay-per-View copy protection system rev. 7.01, rev. 6.1 and rev. 1.03
(525p) as option; this applies to the SAA7104E only
s
Optional cross-color reduction for PAL and NTSC CVBS outputs
s
Power-save modes
s
Joint Test Action Group (JTAG) Boundary Scan Test (BST)
s
Monolithic CMOS 3.3 V device, 5 V tolerant I/Os
3. Quick reference data
Table 1:
Symbol
V
DDA
V
DDD
I
DDA
I
DDD
V
i
V
o(p-p)
Quick reference data
Parameter
analog supply voltage
digital supply voltage
analog supply current
digital supply current
input signal voltage levels
analog CVBS output signal
voltage for a 100/100 color
bar at 75/2
Ω
load
(peak-to-peak value)
load resistance
low frequency integral
linearity error of DACs
low frequency differential
linearity error of DACs
ambient temperature
Conditions
Min
3.15
3.15
1
1
-
Typ
3.3
3.3
110
175
1.23
Max
3.45
3.45
115
200
-
Unit
V
V
mA
mA
V
TTL compatible
R
L
ILE
lf(DAC)
DLE
lf(DAC)
T
amb
-
-
-
0
37.5
-
-
-
-
±3
±1
70
Ω
LSB
LSB
°C
SAA7104E_SAA7105E_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2005
2 of 78
Philips Semiconductors
SAA7104E; SAA7105E
Digital video encoder
4. Ordering information
Table 2:
Ordering information
Name
SAA7104E
SAA7105E
LBGA156
Description
plastic low profile ball grid array package;
156 balls; body 15
×
15
×
1.05 mm
Version
SOT700-1
Type number Package
SAA7104E_SAA7105E_2
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
Product data sheet
Rev. 02 — 23 December 2005
3 of 78
xxxx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxx x xxxxxxxxxxxxxx xxxxxxxxxx xxx xxxxxx xxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx
xxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxxxx xxxxxxxxxxxxxxxxxxx
xxxxxxxxxxxxxxxx xxxxxxxxxxxxxx xxxxxx xx xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxxxxxxxxxxxxxxx xxxxxxx
xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx xxxxxxxxxxx xxxxx x x
Product data sheet
Rev. 02 — 23 December 2005
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SAA7104E_SAA7105E_2
5. Block diagram
Philips Semiconductors
V
DDA1
V
DDA2
B6
V
DDA3
D6
V
DDA4
B6
V
SSA1
B8
V
SSA2
A8
V
DDD1
F4
V
DDD2
D4
V
DDD3
D4
V
DDD4
D4
V
SSD1
V
SSD2
V
SSD3
V
SSD4
C5, D5,
E4
A4
A7, B7
TRST
DUMP
RSET
TDI
TDO
TMS
TCK
A10, B9,
C9, D9
C5, D5, C5, D5,
E4
E4
C5, D5,
E4
PD11 to
PD0
C1, C2, B1, B2,
A2, B4, B3, A3,
F3, H1,
H2, H3
INPUT
FORMATTER
FIFO
+
UPSAMPLING
LUT
+
CURSOR
RGB TO Y-C
B
-C
R
MATRIX
A9
B5
D1
PIXCLKI
F2
DECIMATOR
4 : 4 : 4 to
4:2:2
D3
HORIZONTAL
SCALER
VERTICAL
SCALER
VERTICAL
FILTER
E1
C6
FIFO
BORDER
GENERATOR
VIDEO
ENCODER
TRIPLE
DAC
C7
C8
BLUE_CB_CVBS
GREEN_VBS_CVBS
RED_CR_C_CVBS
SAA7104E; SAA7105E
SAA7104E
SAA7105E
G4
PIXEL CLOCK
SYNTHESIZER
CRYSTAL
OSCILLATOR
A5
XTALI
A6
XTALO
FSVGC
27 MHz
TTX_SRES
CBO
C3
TIMING
GENERATOR
G1 F1 G3 E3
HD
OUTPUT
D7
I
2
C-BUS
CONTROL
C4
G2
E2
D2
D8
F12
VSM
HSM_CSYNC
TVD
mhc572
PIXCLKO
TTXRQ_XCLKO2
SDA
SCL RESET
VSVGC HSVGC
Digital video encoder
4 of 78
Fig 1. Block diagram
Philips Semiconductors
SAA7104E; SAA7105E
Digital video encoder
6. Pinning information
6.1 Pinning
ball A1
index area
1 2 3 4 5 6 7 8 9 10 11 12 13 14
A
B
C
D
E
F
G
H
J
K
L
M
N
P
SAA7104E
SAA7105E
001aad370
Transparent top view
Fig 2. Pin configuration
Table 3:
Pin
A2
A4
A6
A8
A10
B2
B4
B6
B8
C1
C3
C5
C7
C9
D2
D4
D6
D8
E1
E3
Pin allocation table
Symbol
PD7
TRST
XTALO
V
SSA2
V
DDA1
PD8
PD6
V
DDA2
, V
DDA4
V
SSA1
PD11
TTX_SRES
V
SSD1
, V
SSD2
, V
SSD3
, V
SSD4
GREEN_VBS_CVBS
V
DDA1
RESET
V
DDD2
, V
DDD3
, V
DDD4
V
DDA3
HSM_CSYNC
TCK
HSVGC
Pin
A3
A5
A7
A9
B1
B3
B5
B7
B9
C2
C4
C6
C8
D1
D3
D5
D7
D9
E2
E4
Symbol
PD4
XTALI
DUMP
RSET
PD9
PD5
TDI
DUMP
V
DDA1
PD10
TTXRQ_XCLKO2
BLUE_CB_CVBS
RED_CR_C_CVBS
TDO
TMS
V
SSD1
, V
SSD2
, V
SSD3
, V
SSD4
VSM
V
DDA1
SCL
V
SSD1
, V
SSD2
, V
SSD3
, V
SSD4
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
SAA7104E_SAA7105E_2
Product data sheet
Rev. 02 — 23 December 2005
5 of 78
电源技术
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
