b. See reliability manual for profile. The ChipFET/PowerPAK is a leadless package. The end of the lead terminal is exposed copper (not plated)
as a result of the singulation process in manufacturing. A solder fillet at the exposed copper tip cannot be guaranteed and is not required to
ensure adequate bottom side solder interconnection.
c. Rework conditions: manual soldering with a soldering iron is not recommended for leadless components.
Document Number: 71056
S10-0547-Rev. C, 08-Mar-10
www.vishay.com
1
Si5504DC
Vishay Siliconix
SPECIFICATIONS
T
J
= 25 °C, unless otherwise noted
Parameter
Static
Gate Threshold Voltage
Gate-Body Leakage
V
GS(th)
I
GSS
V
DS
= V
GS
, I
D
= 250 µA
V
DS
= V
GS
, I
D
= - 250 µA
V
DS
= 0 V, V
GS
= ± 20 V
V
DS
= 24 V, V
GS
= 0 V
Zero Gate Voltage Drain Current
I
DSS
V
DS
= - 24 V, V
GS
= 0 V
V
DS
= 24 V, V
GS
= 0 V, T
J
= 85 °C
V
DS
= - 24 V, V
GS
= 0 V, T
J
= 85 °C
On-State Drain Current
a
I
D(on)
V
DS
≥
5 V, V
GS
= 10 V
V
DS
≤
- 5 V, V
GS
= - 10 V
V
GS
= 10 V, I
D
= 2.9 A
Drain-Source On-State Resistance
a
R
DS(on)
V
GS
= - 10 V, I
D
= - 2.1 A
V
GS
= 4.5 V, I
D
= 2.2 A
V
GS
= - 4.5 V, I
D
= - 1.6 A
Forward Transconductance
a
Diode Forward Voltage
a
Dynamic
b
Total Gate Charge
Gate-Source Charge
Gate-Drain Charge
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Source-Drain Reverse Recovery Time
Q
g
Q
gs
Q
gd
t
d(on)
t
r
t
d(off)
t
f
t
rr
P-Channel
V
DS
= - 15 V, V
GS
= - 10 V, I
D
= - 2.1 A
N-Ch
N-Channel
V
DS
= 15 V, V
GS
= 10 V, I
D
= 2.9 A
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
N-Channel
V
DD
= 15 V, R
L
= 15
Ω
I
D
≅
1 A, V
GEN
= 10 V, R
g
= 6
Ω
P-Channel
V
DD
= - 15 V, R
L
= 15
Ω
I
D
≅
- 1 A, V
GEN
= - 10 V, R
g
= 6
Ω
I
F
= 0.9 A, dI/dt = 100 A/µs
I
F
= - 0.9 A, dI/dt = 100 A/µs
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
5
5.5
0.8
1.2
1.0
0.9
7
8
12
11
12
14
7
8
40
40
11
12
18
18
18
21
11
12
80
80
ns
7.5
6.6
nC
g
fs
V
SD
V
DS
= 15 V, I
D
= 2.9 A
V
DS
= - 15 V, I
D
= - 2.1 A
I
S
= 0.9 A, V
GS
= 0 V
I
S
= - 0.9 A, V
GS
= 0 V
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
N-Ch
P-Ch
10
- 10
0.072
0.137
0.120
0.240
6
3
0.8
- 0.8
1.2
- 1.2
0.085
0.165
0.143
0.290
S
V
Ω
1.0
- 1.0
± 100
± 100
1
-1
5
-5
A
µA
V
nA
Symbol
Test Conditions
Min.
Typ.
Max.
Unit
Notes:
a. Pulse test; pulse width
≤
300 µs, duty cycle
≤
2 %.
b. Guaranteed by design, not subject to production testing.
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
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