NB3M8T3910G
2.5V/3.3V 3:1:10
Configurable Differential
Clock Fanout Buffer with
LVCMOS Reference Output
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Description
The NB3M8T3910G is a 3:1:10 Clock fanout buffer operating on a
2.5 V/3.3 V Core V
DD
and a flexible 2.5 V / 3.3 V V
DDO
supply
(V
DDO
≤
V
DD
).
A 3:1 MUX selects between Crystal oscillator inputs, or either of
two differential Clock inputs capable of accepting LVPECL, LVDS,
HCSL, or SSTL levels. The MUX select lines, SEL0 and SEL1, accept
LVCMOS or LVTTL levels and select input per Table 3. The Crystal
input is disabled when a Clock input is selected.
Differential Outputs consist of two banks of five differential outputs
with each bank independently mode configurable as LVPECL, LVDS
or HCSL. Each bank of differential output pairs is configured with a
pair of SMODEAx/Bx select lines using LVCMOS or LVTTL levels
per Table 6. Clock input levels and outputs states are determined per
Table 5.
The Single−Ended LVCMOS Output, REFOUT, is synchronously
enabled by the OE_SE control line per Table 4 using LVCMOS /
LVTTL levels. For Clock frequencies above 250 MHz, the REFOUT
line should be disabled.
Features
MARKING
DIAGRAM
1
1 48
QFN48
G SUFFIX
CASE 485AJ
A
WL
YY
WW
G
NB3M8T
3910G
AWLYYWWG
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
ORDERING INFORMATION
See detailed ordering and shipping information on page 19 of
this data sheet.
•
Crystal, Single−Ended or Differential Input Reference
•
•
•
•
•
•
•
•
•
Clocks
Differential Input Pair can Accept: LVPECL, LVDS,
HCSL, SSTL
Two Output Banks: Each has Five Differential Outputs
Configurable as LVPECL, LVDS, or HCSL by
SMODEAx/Bx Pins
One Single−Ended LVCMOS Output with Synchronous
OE Control
LVCMOS/LVTTL Interface Levels for all Control
Inputs
Clock Frequency: Up to 1400 MHz, Typical
Output Skew: 50 ps (Max)
Additive RMS Jitter <0.03 ps (156.25 MHz, Typical)
Input to Output Propagation Delay (900 ps Typical)
Operating Supply Modes V
DD
/V
DDO
: 2.5 V/2.5 V,
3.3 V/3.3 V or 3.3 V/2.5 V
•
Industrial Temperature Range −40°C to 85°C
•
This is a Pb−Free Device
Applications
•
•
•
•
•
•
•
•
•
•
Clock Distribution
Telecom
Networking
Backplane
High End Computing
Wireless and Wired Infrastructure
End Products
Servers
Ethernet Switch/Routers
ATE
Test and Measurement
©
Semiconductor Components Industries, LLC, 2016
1
March, 2016 − Rev. 2
Publication Order Number:
NB3M8T3910/D
NB3M8T3910G
VDDOA
VDD
GND
QA0
SMODEA1
REFOUT
VDDOC
OE_SE
QA0
GND
QA1
SMODEA0
SMODEA1
SEL0
SEL1
CLK0
CLK0
CLK1
CLK1
XTAL_IN
XTAL_OUT
OSC
3:1
Mux
CONTROL
QA1
QA2
QA2
QA3
QA3
QA4
QA4
QB0
QB0
QB1
QB1
QB2
IREF
QB2
QB3
SMODEB0
CONTROL
SMODEB1
QB3
QB4
QB4
BANK B
VDDOB
VDDOC
REFOUT
OE_SE
SYNC
QA4 11
QA4 12
13
GND
14
SMODEA0
15
VDD
16
XTAL_IN
17
XTAL_OUT
18
GND
19
SEL0
20
CLK0
21
CLK0
22
SEL1
23
SMODEB0
24
GND
26 QB4
25 QB4
QA3
9
QA3 10
QA2
QA2
QA0
QA0
QA1
QA1
1
2
3
4
SMODEB1
Exposed
Pad (EP)
IREF
38
GND
37
36 QB0
35 QB0
34 QB1
33 QB1
32 VDDOB
31 QB2
30 QB2
29 VDDOB
28 QB3
27 QB3
BANK A
CLK1
41
GND
48
47
46
45
44
43
42
VDD
40
CLK1
39
VDDOA 5
6
7
NB3M8T3910G
VDDOA 8
Figure 2. QFN−48 Pinout Configuration
(Top View)
Figure 1. Simplified Logic Diagram
Table 1. PIN DESCRIPTION
Default
(Internal
Resistors)
Number
1, 2
3, 4
5, 8
Name
QA0, QA0
QA1, QA1
VDDOA
Type
Output
Output
Power
Description
Bank A differential output pair Q0. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q1. Configurable as LVPECL / LVDS / HCSL
VDDOA Positive Supply pin for Bank A outputs. VDDOA pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01
mF
cap to GND
VDDOB Positive Supply pin for Bank B outputs. VDDOB pins must all be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01
mF
cap to GND
VDDOC Positive Supply pin for REFOUT output. VDDOC pin must be
externally connected to a power supply to guarantee proper operation.
Bypass with 0.01
mF
cap to GND
Bank A differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
Bank A differential output pair Q3. Configurable as LVPECL / LVDS / HCSL
Bank A differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
Ground Supply. All GND pins must be externally connected to power supply
to guarantee proper operation.
29, 32
VDDOB
Power
45
VDDOC
Power
6,7
9,10
11,12
13, 18,
24, 37,
43, 48
14, 47
QA2, QA2
QA3, QA3
QA4, QA4
GND
Output
Output
Output
Power
SMODEA0 /
SMODEA1
Input
Pulldown
Output driver selectors for BANK A. See Table 6 for function.
LVCMOS/LVTTL levels.
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NB3M8T3910G
Table 1. PIN DESCRIPTION
Default
(Internal
Resistors)
Number
15, 42
Name
VDD
Type
Power
Description
VDD Positive Supply pin for core logic. VDD pins must all be externally
connected to a power supply to guarantee proper operation. Bypass with
0.01
mF
cap to GND.
Crystal input / output. XTAL_IN can also be driven by X0, TCX0 or other
external single−ended clock.
16, 17
19, 22
20
21
23,
39
25,26
27,28
30,31
33,34
35,36
38
XTAL_IN,
XTAL_OUT
SEL0
SEL1
CLK0
CLK0
SMODEB0 /
SMODEB1
QB4, QB4
QB3, QB3
QB2, QB2
QB1, QB1
QB0, QB0
IREF
Input
Input
Input
Input
Input
Output
Output
Output
Output
Output
Output
Pulldown
Pulldown
Pullup /
Pulldown
Pulldown
Input clock selectors. See Table 3 for function. LVCMOS/LVTTL interface
levels.
Non−inverting clock input 0. LVPECL, LVDS, SSTL, HCSL levels.
Inverting differential clock input 0. LVPECL, LVDS, SSTL, HCSL, LVCMOS
levels. Internal bias to V
DD
B
2.
Output driver selects for BANK B. See Table 6 for function. LVCMOS/LVTTL
levels.
Bank B differential output pair Q4. Configurable as LVPECL / LVDS / HCSL
Bank B differential output pair Q3. Configurable as LVPECL / LVDS / HCSL.
Bank B differential output pair Q2. Configurable as LVPECL / LVDS / HCSL.
Bank B differential output pair Q1. Configurable as LVPECL / LVDS / HCSL.
Bank B differential output pair Q0. Configurable as LVPECL / LVDS / HCSL.
Connect a fixed 475
W
precision resistor from this pin to ground to provide
the output reference current. Required for HCSL, not used for LVPECL or
LVDS.
40
41
44
46
EP
CLK1
CLK1
REFOUT
OE_SE
EXPOSED
PAD
Input
Input
Output
Input
Thermal
Pullup /
Pulldown
Pulldown
Inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL levels
internal bias to V
DD
/2. Internal bias to V
DD
B
2.
Non−inverting differential clock input 1. LVPECL, LVDS, SSTL, HCSL,
LVCMOS levels.
Reference output, LVCMOS.
Pulldown
Synchronous Enable Control for REFOUT. LVCMOS/LVTTL levels.
The Exposed Pad (EP) on the QFN−48 package bottom is thermally
connected to the die for improved heat transfer out of package. The
exposed pad must be attached to a heat−sinking conduit. The pad is
electrically connected to the die, and must be electrically connected to
GND.
Table 2. PIN CHARACTERISTICS
Symbol
CIN
RPU/RPD
Input Capacitance
Input Pullup/Pulldown Resistor
Parameter
Min
Typ
4
50
Max
Unit
pF
kW
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NB3M8T3910G
FUNCTION TABLES
Table 3. SELx INPUT SELECT TABLE
SEL[1:0] Inputs
00
01
10
11
Selected Input
CLK0/CLK0
CLK1/CLK1
XTAL
XTAL
Table 5. DIFF CLK INPUT / OUTPUT TABLE (Diff or
S.E. stimulus)
Input State
CLKx = LOW, CLKx = HIGH
CLKx = HIGH, CLKx = LOW
CLKx = Open; CLKx = Open
CLKx = LOW; CLKx = LOW
Output State
Qx = LOW, Qx = HIGH
Qx = HIGH, Qx = LOW
Qx = LOW, Qx = HIGH
Qx = LOW, Qx = HIGH
Qx = LOW, Qx = HIGH
Table 4. OE_SE OUTPUT CONTROL TABLE FOR
REFOUT
OE_SE Input Level
Low
High
REFOUT Status
High Impedance
Enabled
CLKx = HIGH; CLKx = HIGH
Table 6. OUTPUT MODE CONFIGURATION TABLE
SMODEA/B[1:0] Inputs
00
01
10
11
Output Mode
LVPECL output.
LVDS output.
HCSL output.
High Impedance.
Table 7. ATTRIBUTES
Characteristic
ESD Protection
Moisture Sensitivity (Note 1)
Flammability Rating
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
1. For additional information, see Application Note AND8003/D.
Human Body Model
Machine Model
QFN48
Oxygen Index: 28 to 34
Value
>2 kV
200 V
Level 1
UL 94 V−0 @ 0.125 in
1318 Devices
Table 8. MAXIMUM RATINGS
(Note 2)
Symbol
V
DD
V
I
V
o
I
o
I
o
V
OHCSL
T
A
T
stg
q
JA
q
JC
T
sol
Positive Power Supply
XTAL_IN Input Voltage
CLKx/CLKx; SELx; SMODExx; OS_SE
Output Voltage
LVPECL Output Current
LVDS Output Current
Output Voltage (HCSL)
Operating Temperature Range, Industrial
Storage Temperature Range
Thermal Resistance (Junction−to−Ambient)
Thermal Resistance (Junction−to−Case)
Soldering Temperature
0 lfpm
500 lfpm
(Note 2)
HCSL; LVCMOS
Continuous Current
Surge Current
Continuous Current
Surge Current
Parameter
Condition
GND = 0 V
Rating
4.6
0
≤
V
I
≤
V
DD
−0.5
≤
V
I
≤
V
DDO
+ 0.5
−0.5
v
V
O
≤
V
DDO
+ 0.5
50
100
10
15
−0.5 to V
DDO
+ 0.5
−40 to 85
−65 to +150
30.5
24.9
12 − 17
+260
Unit
V
V
V
V
mA
mA
V
°C
°C
°C/W
°C/W
°C
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
2. JEDEC standard multilayer board − 2S2P (2 signal, 2 power).
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NB3M8T3910G
DC ELECTRICAL CHARACTERISTICS
Table 9. DC ELECTRICAL CHARACTERISTICS POWER SUPPLY DC CHARACTERISTICS,
GND = 0.0 V; T
A
= −40°C to 85°C
Symbol
V
DD
V
DDOx
I
DD
Parameter
Core Supply Voltage
Output Supply Voltage
Core Supply Current
LVPECL Outputs
LVDS Outputs
HCSL Outputs
All LVPECL Outputs Unloaded
ALL LVDS Outputs Loaded
All HCSL Output Unloaded
Test Conditions
Min
2.375
2.375
85
155
90
50
60
45
Typ
Max
3.465
3.465
120
185
120
70
80
60
Unit
V
V
mA
I
DDO
Output Supply Current
mA
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
Table 10. LVCMOS/LVTTL DC,
V
DD
/V
DDO
= 2.5 V/2.5 V, 3.3 V/3.3 V or 3.3 V/2.5 V
±5%;
GND = 0.0 V; T
A
= −40°C to 85°C
Symbol
V
IH
Parameter
Input High Voltage
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
Input Low Voltage
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
Input High Current
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
Input Low Current
(SEL0/1, SMODEA0/1, SMODEB0/1
OE_SE)
Output High Voltage (Note 3) REFOUT
Output LOW Voltage (Note 3) REFOUT
Test Conditions
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= 3.3 V
V
DD
= 2.5 V
V
DD
= V
IN
= 3.465 V
Min
2
1.7
−0.3
−0.3
0.8
0.7
150
mA
V
Typ
Max
V
DD
+ 0.3
V
DD
+ 0.3
Unit
V
V
IL
I
IH
I
IL
V
DD
= 3.465V, V
IN
= 0 V
−150
mA
V
OH
V
OL
V
DDO
= 3.3 V
±5%
V
DDO
= 2.5 V
±5%
V
DDO
= 3.3 V
±5%
V
DDO
= 2.5 V
±5%
2.3
1.5
0.5
0.4
V
V
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm.
3. Outputs terminated with 50
W
to V
DDO
/2. See Parameter Measurement Information.
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