74VHC165FT
CMOS Digital Integrated Circuits
Silicon Monolithic
74VHC165FT
1. Functional Description
•
8-Bit Shift Register (P-IN, S-OUT)
2. General
The 74VHC165FT is an advanced high speed CMOS 8-BIT PARALLEL/SERIAL-IN, SERIAL-OUT SHIFT
REGISTER fabricated with silicon gate C
2
MOS technology.
It achieves the high speed operation similar to equivalent Bipolar Schottky TTL while maintaining the CMOS
low power dissipation.
It consists of parallel-in or serial-in, serial-out 8-bit shift register with a gated clock input. When the SHIFT/
LOAD input is held high, the serial data input is enabled and the eight frip-frops perform serial shifting with
each clock pulse.
When the SHIFT/LOAD input is held low, the parallel data is loaded synchronously into the register at positive
going transition of the clock pulse.
The CK-INH input should be shifted high only when the CK input is held high.
An Input protection circuit ensures that 0 to 5.5 V can be applied to the input pins without regard to the supply
voltage. This device can be used to interface 5 V to 3 V systems and on two supply systems such as battery back
up. This circuit prevents device destruction due to mismatched supply and input voltages.
3. Features
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
AEC-Q100 (Rev. H) (Note 1)
Wide operating temperature range: T
opr
= -40 to 125
High speed: f
MAX
= 150 MHz (typ.) at V
CC
= 5 V
Low power dissipation: I
CC
= 4.0
µA
(max) at T
a
= 25
High noise immunity: V
NIH
= V
NIL
= 28 % V
CC
(min)
Power-down protection is provided on all inputs.
Balanced propagation delays: t
PLH
≈
t
PHL
Wide operating voltage range: V
CC(opr)
= 2.0 V to 5.5 V
(9) Pin and function compatible with 74 series (74AC/HC/AHC etc.) 165 type.
Note 1: This device is compliant with the reliability requirements of AEC-Q100. For details, contact your Toshiba sales
representative.
Start of commercial production
©2016 Toshiba Corporation
1
2013-05
2016-08-18
Rev.4.0
74VHC165FT
7. IEC Logic Symbol
8. Truth Table
X:
Don't care
a.....h: The level of steady state input voltage at inputs A through H respectively.
QAn to QGn: The level of QA to QG, respectively, before the most recent positive transition of the CK.
©2016 Toshiba Corporation
3
2016-08-18
Rev.4.0
嵌入式系统
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