TMC2249A
Digital Mixer
12 x 12 Bit, 60 MHz
Features
•
•
•
•
•
•
•
•
•
60 MHz input and computation rate
Two 12-bit multipliers
Separate data and coefficient inputs
Independent, user-selectable pipeline delays of 1 to 16
clocks on all input ports
Separate 16-bit input port allows cascading or addition of
a constant
User-selectable rounded output
Internal 1/2 LSB rounding of products
Fully registered, pipelined architecture
Available in 120-Pin CPGA, PPGA, MPGA or MQFP
Applications
•
•
•
•
•
•
Video switching
Image mixing
Digital signal modulation
Complex frequency synthesis
Digital filtering
Complex arithmetic functions
Description
The TMC2249A is a high-speed digital arithmetic circuit
consisting of two 12-bit multipliers, an adder and a cascade-
able accumulator. All four multiplier inputs are simulta-
neously accessible to the user, and each includes a user-
programmable pipeline delay of up to 16 clocks in length.
The 24-bit adder/subtractor is followed by an accumulator
and 16-bit input port which allows the user to cascade multi-
ple TMC2249As. A new 16-bit accumulated output is avail-
able every clock, up to the maximum rate of 60 MHz. All
inputs and outputs are registered except the three-state out-
put enable, and all are TTL compatible.
The TMC2249A utilizes a pipelined, bus-oriented structure
offering significant flexibility. Input register clock enables
and programmable input data pipeline delays on each port
offer an adaptable input structure for high-speed digital
systems. Following the multipliers, the user may perform
addition or subtraction of either product, arithmetic rounding
to 16 bits, and accumulation and summation of products with a
cascading input. The output port allows access to all 24 bits of
the internal accumulator by switching between overlapping
least and most-significant 16-bit words, and a three-state out-
put enable simplifies connection to an external system bus.
The TMC2249A has numerous applications in digital pro-
cessing algorithms, from executing simple image mixing and
switching, to performing complex arithmetic functions and
complex waveform synthesis. FIR filters, digital quadrature
mixers and modulators, and vector arithmetic functions may
also be implemented with this device.
Fabricated in a submicron CMOS process, the TMC2249A
operates at guaranteed clock rates of up to 60 MHz over the
full temperature and supply voltage ranges. It is pin- and
function-compatible with CADEKA’s TMC2249, while pro-
viding higher speed operation and lower power dissipation. It
is available in a 120 pin Ceramic Pin Grid Array (CPGA),
120 pin Plastic Pin Grid Array (PPGA), 120 lead MQFP to
PPGA package (MPGA), and a 120 lead Metric Quad Flat-
Pack (MQFP).
Logic Symbol
TMC2249A
Digital Mixer
A
11-0
ADEL
3-0
ENA
B
11-0
BDEL
3-0
ENB
C
11-0
CDEL
3-0
ENC
D
11-0
DDEL
3-0
END
CAB
15-0
Delay
1-16
Delay
1-16
Delay
1-16
Delay
1-16
RND
FT
CASEN
CLK
NEG1
NEG2
SWAP
OE
ACC
S
15-0
REV. 1.0.2 7/6/00
TMC2249A
PRODUCT SPECIFICATION
Functional Description
The TMC2249A performs the summation of products
described by the formula:
S(N+5) =A(N-ADEL)
×
B(N-BDEL)
×
(-1
NEG1(N)
) +
C(N-CDEL)
×
D(N-DDEL)
×
(-1
NEG2(N)
) +
CAS(N+3
×
FT)
where ADEL through DDEL range from 1 to 16 pipe delays.
All inputs and controls utilize pipeline delay registers to
maintain synchronicity with the data input during that clock,
except when the Cascade data input is routed directly to the
accumulator by use of the Feedthrough control. One-half
LSB rounding to 16 bits may be performed on the sum of
products while summing with the cascade input data.
The user may access either the upper or lower 16 bits of the
24-bit accumulator by swapping overlapping registers. The
output bus has an asynchronous high-impedance enable, to
simplify interfacing to complex systems.
Pin Assignments
120 Pin Metric Quad Flat Pack, KE Package
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Name
CLK
ACC
NEG1
NEG2
RND
S15
S14
GND
S13
S12
S11
VDD
S10
S9
S8
GND
S7
S8
S5
VDD
S4
S3
S2
GND
S1
S0
OE
SWAP
BDEL0
BDEL1
Pin
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
Name
BDEL2
BDEL3
ENB
B0
B1
B2
B3
B4
B5
B6
B7
GND
B8
B9
B10
VDD
B11
A11
A10
A9
A8
A7
A6
A5
A4
A3
A2
A1
A0
ENA
Pin
61
62
63
64
65
66
67
68
69
70
71
72
73
74
75
76
77
78
79
80
81
82
83
84
85
86
87
88
89
90
Name
ADEL3
ADEL2
ADEL1
ADEL0
NC
CAS15
CAS14
CAS13
CAS12
CAS11
CAS10
GND
CAS9
CAS8
CAS7
CAS6
CAS5
CAS4
CAS3
CAS2
CAS1
CAS0
CASEN
FT
CDEL0
CDEL1
CDEL2
CDEL3
ENC
C0
Pin
91
92
93
94
95
96
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
Name
C1
C2
C3
C4
C5
C6
C7
C8
C9
C10
C11
VDD
D11
D10
D9
GND
D8
D7
D6
D5
D4
D3
D2
D1
D0
END
DDEL3
DDEL2
DDEL1
DDEL0
1
120
91
90
30
31
61
60
REV. 1.0.2 7/6/00
3
TMC2249A
PRODUCT SPECIFICATION
Pin Descriptions
Pin Number
Pin Name CPGA/PPGA/
MPGA
Power
V
DD
GND
Clock
CLK
C3
1
System Clock.
The TMC2249A operates from a single master
clock input. The rising edge of clock strobes all enabled registers.
All timing specifications are referenced to the rising edge of CLK.
A-D Input.
A through D are the four 12-bit registered data input
ports. A
0
-D
0
are the LSBs (see Table 1). Data presented to the input
ports is clocked in to the top of the 16-stage delay pipeline on the
next clock when enabled, "pushing" data down the register stack.
F3, H3, L7, C8 12, 20, 46, 102
Supply Voltage.
The TMC2249A operates from a single +5V
supply. All power and ground pins must be connected.
E3, G3, J3, L6,
H11, C7
8, 16, 24, 42,
72, 106
Ground.
The TMC2249A operates from a single +5V supply. All
power and ground pins must be connected.
MQFP
Pin Function Description
Inputs
A
11-0
N8, M8, L8, 48, 49, 50, 51,
N9, M9, N10, 52, 53, 54, 55,
L9, M10, N11, 56, 57, 58, 59
N12, L10, M11
N7, M7, N6,
M6, N5, M5,
N4, L5, M4,
N3, M3, L4
47, 45, 44, 43,
41, 40, 39, 38,
37, 36, 35, 34
B
11-0
C
11-0
A9, B9, A10, 101, 100, 99,
C9, B10, A11, 98, 97, 96, 95,
B11, C10, A12, 94, 93, 92, 91,
B12, C11, A13
90
B8, A8, B7, A7, 103, 104, 105,
A6, B6, C6, A5, 107, 108, 109,
B5, A4, C5, B4 110, 111, 112
113, 114, 115
L11, M12,
M13, K11
D11, B13,
C13, D12
61, 62, 63, 64
A-D Delay.
ADEL through DDEL are the four-bit registered input
data pipe delay select word inputs. Data to be presented to the
multipliers is selected from one of sixteen stages in the input data
delay pipe registers, as indicated by the delay select word
presented to the respective input port during that clock. The
minimum delay is one clock (select word=0000), and the maximum
delay is 16 clocks (select word=1111). Following powerup these
values are indeterminate and must be initialized by the user.
Cascade Input.
CAS is the 16-bit Cascade data input port. CAS
0
is
the LSB. See Table 1.
D
11-0
ADEL
3-0
BDEL
3-0
CDEL
3-0
DDEL
3-0
CAS
15-0
M2, L3, N1, L2 32, 31, 30, 29
88, 87, 86, 85
A2, C4, B3, A1 117, 118, 119,
120
L13, K12, J11,
K13, J12, J13,
H12, H13,
G12, G11,
G13, F13, F12,
F11, E13, E12
66, 67, 68, 69,
70, 71, 73, 74,
75, 76, 77, 78,
79, 80, 81, 82
Controls
S
15-0
C1, D2, D1, 6, 7, 9, 10, 11,
E2, E1, F2, F1, 13, 14, 15, 17,
G2, G1, H1, 18, 19, 21, 22,
H2, J1, J2, K1,
23, 25, 26
K2, L1
Sum Output.
The current 16-bit result is available at the Sum
output. The output may be the most or least significant 16 bits of the
current accumulator output, as determined by SWAP. S
0
is the LSB.
See Table 1.
REV. 1.0.2 7/6/00
5
嵌入式系统
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
