74LVCH32374A
32-bit edge-triggered D-type flip-flop with 5 V tolerant
inputs/outputs; 3-state
Rev. 3 — 18 December 2012
Product data sheet
1. General description
The 74LVCH32374A is a 32-bit edge-triggered flip-flop featuring separate D-type inputs
for each flip-flop and 3-state outputs for bus oriented applications. The device consists of
4 sections of 8 edge-triggered flip-flops. A clock (pin nCP) input and an output enable
input (pin nOE) are provided per 8-bit section. The flip-flops will store the state of their
individual D-inputs that meet the set-up and hold time requirements on the LOW-to-HIGH
nCP transition. When pin nOE is LOW, the contents of the flip-flops are available at the
outputs. When pin nOE is HIGH, the outputs go to the high-impedance OFF-state.
Operation of pin nOE does not affect the state of the flip-flops. The inputs can be driven
from either 3.3 V or 5 V devices. In 3-state operation, the outputs can handle 5 V. These
features allow the use of these devices in a mixed 3.3 V or 5 V environment.
Bus hold on data inputs eliminates the need for external pull-up resistors to hold unused
inputs.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Multiple low inductance supply pins for minimum noise and ground bounce
Direct interface with TTL levels
All data inputs have bus hold
High impedance when V
CC
= 0 V
Latch-up performance exceeds 500 mA per JESD 78 Class II
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and
40 C
to +125
C
Packaged in plastic fine-pitch ball grid array package
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVCH32374AEC
40 C
to +125
C
Name
LFBGA96
Description
plastic low profile fine-pitch ball grid array package;
96 balls; body 13.5
5.5
1.05 mm
Version
SOT536-1
Type number
4. Functional diagram
1D0
D
CP
FF 1
Q
1Q0
2D0
D
CP
FF 9
Q
2Q0
1CP
1OE
to 7 other channels
2CP
2OE
to 7 other channels
3D0
D
CP
Q
3Q0
4D0
D
CP
Q
4Q0
FF 17
FF 25
3CP
3OE
to 7 other channels
4CP
4OE
to 7 other channels
coa012
Fig 1.
Logic symbol
V
CC
data
input
to internal circuit
mna473
Fig 2.
Bus hold circuit
74LVCH32374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2012
2 of 15
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
5. Pinning information
5.1 Pinning
001aah180
6
5
4
3
2
1
1D1 1D3 1D5 1D7 2D1 2D3 2D5 2D6 3D1 3D3 3D5 3D7 4D1 4D3 4D5 4D6
1D0 1D2 1D4 1D6 2D0 2D2 2D4 2D7 3D0 3D2 3D4 3D6 4D0 4D2 4D4 4D7
1CP GND V
CC
GND GND V
CC
GND 2CP 3CP GND V
CC
GND GND V
CC
GND 4CP
1OE GND V
CC
GND GND V
CC
GND 2OE 3OE GND V
CC
GND GND V
CC
GND 4OE
1Q0 1Q2 1Q4 1Q6 2Q0 2Q2 2Q4 2Q7 3Q0 3Q2 3Q4 3Q6 4Q0 4Q2 4Q4 4Q7
1Q1 1Q3 1Q5 1Q7 2Q1 2Q3 2Q5 2Q6 3Q1 3Q3 3Q5 3Q7 4Q1 4Q3 4Q5 4Q6
A
B
C
D
E
F
G
H
J
K
L
M
N
P
R
T
Fig 3.
Pin configuration
5.2 Pin description
Table 2.
Symbol
nOE (n = 1 to 4)
nCP (n = 1 to 4)
1D[0:7]
2D[0:7]
3D[0:7]
4D[0:7]
1Q[0:7]
2Q[0:7]
3Q[0:7]
4Q[0:7]
GND
V
CC
Pin description
Ball
A3, H3, J3, T3
A4, H4, J4, T4
A5, A6, B5, B6, C5, C6, D5, D6
E5, E6, F5, F6, G5, G6, H6, H5
J5, J6, K5, K6, L5, L6, M5, M6
N5, N6, P5, P6, R5, R6, T6, T5
A2, A1, B2, B1, C2, C1, D2, D1
E2, E1, F2, F1, G2, G1, H1, H2
J2, J1, K2, K1, L2, L1, M2, M1
N2, N1, P2, P1, R2, R1, T1, T2
B3, B4, D3, D4, E3, E4, G3, G4, K3, K4, M3,
M4, N3, N4, R3, R4
C3, C4, F3, F4, L3, L4, P3, P4
Description
output enable input (active LOW)
clock input
data input
data input
data input
data input
data output
data output
data output
data output
ground (0 V)
supply voltage
74LVCH32374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2012
3 of 15
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
6. Functional description
Table 3.
Function table
[1]
Input
nOE
Load and read
register
Load register and
disable outputs
[1]
Operating mode
Internal flip-flop
nCP
nDn
l
h
l
h
L
H
L
H
Output
nQn
L
H
Z
Z
L
L
H
H
H = HIGH voltage level
L = LOW voltage level
h = HIGH voltage level one set-up time prior to the HIGH-to-LOW CP transition
l = LOW voltage level one set-up time prior to the HIGH-to-LOW CP transition
Z = high-impedance OFF-state
= LOW-to-HIGH CP transition
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V)
[1]
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
[4]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0
[2]
Min
0.5
50
0.5
-
[3]
[3]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
200
-
+150
1000
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
200
65
T
amb
=
40 C
to +125
C
[4]
-
All supply and ground pins connected externally to one voltage source.
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
Above 70
C
the value of P
tot
derate linearly with 1.8 mW/K.
74LVCH32374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2012
4 of 15
NXP Semiconductors
74LVCH32374A
32-bit edge-triggered D-type flip-flop; 5 V tolerant; 3-state
8. Recommended operating conditions
Table 5.
Symbol
V
CC
V
I
V
O
T
amb
t/V
Recommended operating conditions
Parameter
supply voltage
functional
input voltage
output voltage
ambient temperature
input transition rise and fall rate
output HIGH or LOW state
output 3-state
in free air
V
CC
= 1.65 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
Conditions
Min
1.65
1.2
0
0
0
40
-
-
Typ
-
-
-
-
-
-
-
-
Max
3.6
3.6
5.5
V
CC
5.5
+125
20
10
Unit
V
V
V
V
V
C
ns/V
ns/V
9. Static characteristics
Table 6.
Static characteristics
At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).
Symbol Parameter
V
IH
HIGH-level
input voltage
Conditions
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
IL
LOW-level
input voltage
V
CC
= 1.2 V
V
CC
= 1.65 V to 1.95 V
V
CC
= 2.3 V to 2.7 V
V
CC
= 2.7 V to 3.6 V
V
OH
HIGH-level
output voltage
V
I
= V
IH
or V
IL
I
O
=
100 A;
V
CC
= 1.65 V to 3.6 V
I
O
=
4
mA; V
CC
= 1.65 V
I
O
=
8
mA; V
CC
= 2.3 V
I
O
=
12
mA; V
CC
= 2.7 V
I
O
=
18
mA; V
CC
= 3.0 V
I
O
=
24
mA; V
CC
= 3.0 V
V
OL
LOW-level
output voltage
V
I
= V
IH
or V
IL
I
O
= 100
A;
V
CC
= 1.65 V to 3.6 V
I
O
= 4 mA; V
CC
= 1.65 V
I
O
= 8 mA; V
CC
= 2.3 V
I
O
= 12 mA; V
CC
= 2.7 V
I
O
= 24 mA; V
CC
= 3.0 V
I
I
input leakage
current
V
CC
= 3.6 V;
V
I
= 5.5 V or GND
[2]
-
-
-
-
-
-
-
-
-
-
-
0.1
0.2
0.45
0.6
0.4
0.55
5
-
-
-
-
-
-
0.3
0.65
0.8
0.6
0.8
20
V
V
V
V
V
A
V
CC
0.2
1.2
1.8
2.2
2.4
2.2
-
-
-
-
-
-
-
-
-
-
-
V
CC
0.3
1.05
1.65
2.05
2.25
2.0
-
-
-
-
-
-
V
V
V
V
V
V
1.08
1.7
2.0
-
-
-
-
40 C
to +85
C
Min
Typ
[1]
-
-
-
-
-
-
-
-
-
-
-
0.12
0.7
0.8
Max
40 C
to +125
C
Min
1.08
1.7
2.0
-
-
-
-
-
-
0.12
0.7
0.8
0.65
V
CC
-
Max
V
V
V
V
V
V
V
Unit
0.65
V
CC
-
0.35
V
CC
-
0.35
V
CC
V
74LVCH32374A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2012. All rights reserved.
Product data sheet
Rev. 3 — 18 December 2012
5 of 15
嵌入式系统
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