74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin, 30
series termination
resistors; 5 V tolerant input/output; 3-state
Rev. 6 — 23 November 2011
Product data sheet
1. General description
The 74LVC162245A; 74LVCH162245A are 16-bit transceivers with non-inverting 3-state
bus compatible outputs in both send and receive directions. Two send/receive (nDIR)
inputs control direction, and two output enable (nOE) inputs make cascading easy. The
nOE inputs control the outputs so that the buses are effectively isolated. This device can
be used as two 8-bit transceivers or one 16-bit transceiver.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V and 5 V applications.
The 74LVCH162245A bus hold on data inputs eliminates the need for external pull-up
resistors to hold unused inputs.
Both HIGH and LOW output stages include 30
series termination resistors to reduce
line noise.
2. Features and benefits
5 V tolerant inputs/outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Multibyte flow-through standard pin-out architecture
Low inductance multiple power and ground pins for minimum noise and ground
bounce
Direct interface with TTL levels
Integrated 30
termination resistors
High-impedance when V
CC
= 0 V
All data inputs have bus hold (74LVCH162245A only)
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-B exceeds 200 V
CDM JESD22-C101E exceeds 1000 V
Specified from
40 C
to +85
C
and from
40 C
to +125
C
NXP Semiconductors
74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30
resistors; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC162245ADL
74LVCH162245ADL
74LVC162245ADGG
74LVCH162245ADGG
40 C
to +125
C
TSSOP48
40 C
to +125
C
Name
SSOP48
Description
plastic shrink small outline package; 48 leads;
body width 7.5 mm
plastic thin shrink small outline package;
48 leads; body width 6.1 mm
Version
SOT370-1
SOT362-1
Type number
4. Functional diagram
1DIR
1
48
2DIR
1OE
2A0
2
1B0
2A1
3
1B1
2A2
5
1B2
2A3
6
1B3
2A4
8
1B4
2A5
9
1B5
2A6
11
1B6
2A7
12
1B7
24
25
36
13
35
14
33
16
32
17
30
19
29
20
27
22
26
23
2B7
2B6
2B5
2B4
2B3
2B2
2B1
2B0
2OE
1A0
47
1A1
46
1A2
44
1A3
43
1A4
41
1A5
40
1A6
38
1A7
37
mna708
Fig 1.
Logic symbol
74LVC_LVCH162245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 23 November 2011
2 of 16
NXP Semiconductors
74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30
resistors; 3-state
1OE
1DIR
48
1
25
2OE
24
2DIR
G3
3EN1 [BA]
3EN2 [AB]
G6
6EN4 [BA]
6EN5 [AB]
1
2
2
3
5
6
8
9
11
12
4
5
13
14
16
17
19
20
22
23
1B0
1B1
1B2
1B3
1B4
1B5
1B6
1B7
2B0
2B1
2B2
2B3
2B4
2B5
2B6
2B7
1A0
1A1
1A2
1A3
1A4
1A5
1A6
1A7
2A0
2A1
2A2
2A3
2A4
2A5
2A6
2A7
47
46
44
43
41
40
38
37
36
35
33
32
30
29
27
26
mna709
Fig 2.
IEC logic symbol
V
CC
data input
to internal circuit
mna705
Fig 3.
Bus hold circuit
74LVC_LVCH162245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 23 November 2011
3 of 16
NXP Semiconductors
74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30
resistors; 3-state
5. Pinning information
5.1 Pinning
74LVC162245A
74LVCH162245A
1DIR
1B0
1B1
GND
1B2
1B3
V
CC
1B4
1B5
1
2
3
4
5
6
7
8
9
48
1OE
47
1A0
46
1A1
45
GND
44
1A2
43
1A3
42
V
CC
41
1A4
40
1A5
39
GND
38
1A6
37
1A7
36
2A0
35
2A1
34
GND
33
2A2
32
2A3
31
V
CC
30
2A4
29
2A5
28
GND
27
2A6
26
2A7
25
2OE
001aaa156
GND
10
1B6
11
1B7
12
2B0
13
2B1
14
GND
15
2B2
16
2B3
17
V
CC
18
2B4
19
2B5
20
GND
21
2B6
22
2B7
23
2DIR
24
Fig 4.
Pin configuration SSOP48 and TSSOP48
5.2 Pin description
Table 2.
Name
1DIR
2DIR
GND
V
CC
1OE
2OE
1A[0:7]
2A[0:7]
1B[0:7]
2B[0:7]
74LVC_LVCH162245A
Pin description
Pin
1
24
4, 10, 15, 21, 28, 34, 39, 45
7, 18, 31, 42
48
25
47, 46, 44, 43, 41, 40, 38, 37
36, 35, 33, 32, 30, 29, 27, 26
2, 3, 5, 6, 8, 9, 11, 12
13, 14, 16, 17, 19, 20, 22, 23
Description
direction control input
direction control input
ground (0 V)
supply voltage
output enable input (active LOW)
output enable input (active LOW)
data input/output
data input/output
data input/output
data input/output
© NXP B.V. 2011. All rights reserved.
All information provided in this document is subject to legal disclaimers.
Product data sheet
Rev. 6 — 23 November 2011
4 of 16
NXP Semiconductors
74LVC162245A; 74LVCH162245A
16-bit transceiver with direction pin; 30
resistors; 3-state
6. Functional description
Table 3.
Input
nOE
L
L
H
[1]
H = HIGH voltage level
L = LOW voltage level
X = don’t care
Z = high-impedance OFF-state
Function table
[1]
Output
nDIR
L
H
X
nAn
A=B
inputs
Z
nBn
inputs
B=A
Z
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
I
IK
V
I
I
OK
V
O
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input clamping current
input voltage
output clamping current
output voltage
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
V
I
< 0 V
[1]
Min
0.5
50
0.5
-
[2]
[2]
Max
+6.5
-
+6.5
50
V
CC
+ 0.5
+6.5
50
100
-
+150
500
Unit
V
mA
V
mA
V
V
mA
mA
mA
C
mW
V
O
> V
CC
or V
O
< 0 V
output HIGH or LOW state
output 3-state
V
O
= 0 V to V
CC
0.5
0.5
-
-
100
65
T
amb
=
40 C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
Above 60
C
the value of P
tot
derates linearly with 5.5 mW/K.
74LVC_LVCH162245A
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 6 — 23 November 2011
5 of 16
嵌入式系统
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