The LV8498CT is a constant current driver IC for voice coil motors that supports I
2
C control integrating a
digital/analog converter (DAC). It uses an ultraminiature WLP package and includes a current detection resistor for
constant current control, which makes the IC ideal for miniaturization of camera modules intended for use in
camera-equipped mobile phones. The output transistor has a low on-resistance of 1Ω and the resistance of the built-in
current detection resistor is 1Ω, which minimizes the voltage loss and helps withstand voltage drop in VCC. The
function is incorporated, which, by changing the current in a stepped pattern while taking time at rise and fall of the
output current, provides the current a slope, improving the converging stability of the voice coil motor (current slope
function).
Functions
•
Constant current driver for voice coil motors.
•
Constant current control enabled by DAC (10 bits).
2
•
I C bus control supported.
•
Wide operating voltage range (2.2 to 5.0V).
•
Built-in current detection resistor.
•
6-pin WLP package used (1.27
×
0.87
×
0.25mm).
•
Built-in voltage drop protection circuit (VCC = 2V output off).
•
Built-in thermal protection circuit.
•
Low output block total-resistance of 2Ω helps withstand voltage drop in VCC. (Current detection resistance + output
transistor on-resistance).
•
Built-in VCM overshoot preventive function (current slope function).
Specifications
Absolute Maximum Ratings
at Ta = 25°C
Parameter
Maximum supply voltage
Output voltage
Input voltage
GND pin source current
Allowable power dissipation
Operating temperature
Storage temperature
Symbol
VCC max
VOUT max
VIN max
IGND
Pd max
Topr
Tstg
With specified substrate *
SCL, SDA, ENA
Conditions
Ratings
5.5
VCC + 0.5
5.5
200
350
-30 to +85
-40 to +150
Unit
V
V
V
mA
mW
°C
°C
* Specified substrate : 40mm
×
40mm
×
1.6mm, Single layer glass epoxy substrate
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating
Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
Semiconductor Components Industries, LLC, 2013
June, 2013
53011 SY/52511 SY/31710 SY 20091119-S00001 No.A1625-1/8
LV8498CT
Allowable Operating Conditions
at Ta = 25°C
Parameter
Supply voltage
Maximum preset output current
Input signal voltage
Symbol
VCC
IO
VIN
Conditions
Ratings
2.2 to 5.0
150
-0.3 to VCC+0.3
Unit
V
mA
V
Electrical Characteristics
at Ta = 25°C, VCC = 2.8V
Parameter
Supply current
Symbol
ICC0a
ICC0b
ICC0c
ICC1
Input current
High level input voltage
Low level input voltage
Total resistance value of the output block
(built-in resistor + transistor on-resistance)
DAC block
Resolution
Relative accuracy
Differential linearity
Full code current
Error code current 0
Spark killer diode
Reverse current
Forward voltage
IS (leak)
VSF
IOUT=100mA
1
1.3
μA
V
INL
DNL
Ifull
Izero
D0 to D9 = 1
D0 to D9 = 0
150
0
10
±2
±1
bits
LSB
LSB
mA
mA
IIN
VIH
VIL
RTTL
VCC = 2.8V, IOUT = 80mA
Conditions
min
ENA = 0V, SCL=SDA=VCC
ENA=SCL=SDA=VCC, PD = 1
ENA=SCL=SDA=VCC, D0 to D9 = 0
ENA=SCL=SDA=VCC , D0 to D9
≠
0
SCL, SDA, ENA
Applied to SCL, SDA and ENA pin.
-1
1.5
-0.3
2
0.5
0
Ratings
typ
max
1
1
1
3
1
VCC-0.3
0.5
3
μA
μA
μA
mA
μA
V
V
Ω
Unit
Package Dimensions
unit : mm (typ)
3390
TOP VIEW
0.87
SIDE VIEW
BOTTOM VIEW
0.4
Pd max -- Ta
Specified board : 40
×
40
×
1.6mm
3
Single layer glass epoxy
Allowable power dissipation, Pd max -- W
0.235
0.35
0.3
1.27
2
1
0.4
3
B
0.22
SIDE VIEW
0.4
A
0.235
0.2
0.18
0.33 MAX
0.1
0.08
0
--30 --20
0
20
40
60
80
100
120
Ambient temperature, Ta --
°C
SANYO : WLP6K(1.27X0.87)
No.A1625-2/8
LV8498CT
Pin Assignment
Bottom View ( Ball side up )
3
0.4
2
1
Pin No.
A1
A2
A3
Pin Name
SCL
ENA
GND
SDA
VCC
OUT
2
Pin Description
I C SCL input pin
Enable & reset *1, 2
Ground
I
2
C SDA input pin
Power supply pin
Output pin
A
0.4
0.87
B
B1
B2
B3
1.27
*1 : Setting the ENA pin to low powers down and resets the IC.
It is necessary to power on the IC by setting the ENA pin to
low and hold it high during normal operation.
*2 : When the ENA pin is to be used with pull_up, it is necessary to
send code 0 in advance after power-on.
Block Diagram
VCC
ENA
Bias
RESET
ON/OFF
Reference
voltage
Voltage drop protection
&
thermal protection
VCM
SDA
SCL
IC
IF
2
IC
DECODE
2
DAC
10bit
current
setting
+
-
OUT
RF
Timing genaration
GND
No.A1625-3/8
LV8498CT
Serial Bus Communication Specifications
I
2
C serial transfer timing conditions
Standard mode
twH
SCL
twL
th2
SDA
th1
ts2
ts1
ts3
th1
tbuf
Start condition
ton
tof
Resend start condition
Stop condition
Input waveform condition
Standard mode
Parameter
SCL clock frequency
Data setup time
symbol
fscl
ts1
ts2
ts3
Data hold time
th1
th2
Pulse width
twL
twH
Input waveform conditions
ton
tof
Bus free time
tbuf
SCL clock frequency
Setup time of SCL with respect to the falling edge of SDA
Setup time of SDA with respect to the rising edge of SCL
Setup time of SCL with respect to the rising edge of SDA
Hold time of SCL with respect to the rising edge of SDA
Hold time of SDA with respect to the falling edge of SCL
SCL low period pulse width
SCL high period pulse width
SCL, SDA (input) rising time
SCL, SDA (input) falling time
Interval between stop condition and start condition
4.7
Conditions
min
0
4.7
250
4.0
4.0
0
4.7
4.0
1000
300
typ
max
100
unit
kHz
μs
ns
μs
μs
μs
μs
μs
ns
ns
μs
High-speed mode
Parameter
SCL clock frequency
Data setup time
Symbol
fscl
ts1
ts2
ts3
Data hold time
th1
th2
Pulse width
twL
twH
Input waveform conditions
ton
tof
Bus free time
tbuf
SCL clock frequency
Setup time of SCL with respect to the falling edge of SDA
Setup time of SDA with respect to the rising edge of SCL
Setup time of SCL with respect to the rising edge of SDA
Hold time of SCL with respect to the rising edge of SDA
Hold time of SDA with respect to the falling edge of SCL
SCL low period pulse width
SCL high period pulse width
SCL, SDA (input) rising time
SCL, SDA (input) falling time
Interval between stop condition and start condition
1.3
Conditions
min
0
0.6
100
0.6
0.6
0
1.3
0.6
300
300
typ
max
400
unit
kHz
μs
ns
μs
μs
μs
μs
μs
ns
ns
μs
No.A1625-4/8
LV8498CT
I
2
C bus transmission method
Start and stop conditions
The I
2
C bus requires that the state of SDA be preserved while SCL is high as shown in the timing diagram below during a
data transfer operation.
SCL
SDA
ts2
th2
When data is not being transferred, both SCL and SDA are in the high state. The start condition is generated and access is
started when SDA is changed from high to low while SCL and SDA are high.
Conversely, the stop condition is generated and access is ended when SDA is changed from low to high while SCL is
high.
Start condition
Stop condition
SCL
SDA
th1
th3
Data transfer and acknowledgement response
After the start condition has been generated, the data is transferred one byte (8 bits) at a time. Generally, in an I
2
C bus, a
unique 7-bit slave address is assigned to each device, and the first byte of the transfer data is allocated to the 7-bit slave
address and to the command (R/W) indicating the transfer direction of the subsequent data. However, this IC is provided
with only a write mode for receiving the data. Every time 8 bits of data for each byte are transferred, the ACK signal is
sent from the receiving end to the sending end. Immediately after the clock pulse of SCL bit 8 in the data transferred has
fallen to low, SDA at the sending end is released, and SDA is set to low at the receiving end, causing the ACK signal to be
sent. When, after the receiving end has sent the ACK signal, the transfer of the next byte remains in the receiving status,
the receiving end releases SDA at the falling edge of the ninth SCL clock.
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