Short Form Data Sheet
June 2012
5 or 10 Output Any-Rate Clock Multipliers
General Description
The MAX24405 and MAX24410 are flexible, high-
performance clock multiplier/synthesizer ICs with two
independent APLLs. Each APLL performs any-to-any
frequency conversion. From any input clock frequency
9.72MHz to 750MHz these devices can produce
frequency-locked APLL output frequencies up to
750MHz and as many as 10 differential output clock
signals that are integer divisors of the APLL
frequencies. Output jitter is typically 0.35 to 0.5ps RMS
(12kHz to 20MHz) on all outputs and can be as low as
0.24ps RMS. Each device can configure itself from an
external EEPROM so that clock signals are available
immediately after power-up or reset.
MAX24405, MAX24410
Features
♦
Input Clocks
♦
♦
♦
♦
One Crystal or CMOS Input
Three Differential or CMOS Inputs
Differential to 750MHz, CMOS to 125MHz
Clock Selection By Pin or Register Control
APLLs Perform High Resolution Fractional-N
Clock Multiplication
Any Output Frequency from <1Hz to 750MHz
Each Output Has an Independent Divider
Output Jitter 0.35 to 0.5ps RMS Typical on All
Outputs, Can Be As Low As 0.24ps RMS
Outputs are CML or 2xCMOS, Can Interface to
LVDS, LVPECL, HSTL, SSTL and HCSL
CMOS Output Voltage from 1.5V to 3.3V
Automatic Self-Configuration at Power-Up
from External EEPROM Memory
SPI™ Processor Interface
1.8V + 3.3V Operation (5V Tolerant)
-40 to +85
°C
Operating Temp. Range
♦
Two APLLs Plus 5 or 10 Output Clocks
♦
♦
♦
♦
♦
♦
Applications
Frequency Conversion and Synthesis Applications in a
Wide Variety of Equipment Types
♦
General Features
♦
♦
♦
♦
Ordering Information
PART
MAX24405EXG+
MAX24410EXG+
OUTPUTS
5
10
PIN-PACKAGE
81-CSBGA (10mm)
2
81-CSBGA (10mm)
2
Block Diagram
APLL1
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
A
DIV1
DIV2
DIV3
DIV4
DIV5
DIV6
DIV7
DIV8
DIV9
DIV10
OC1POS/NEG
OC2POS/NEG
OC3POS/NEG
OC4POS/NEG
OC5POS/NEG
OC6POS/NEG
OC7POS/NEG
OC8POS/NEG
OC9POS/NEG
OC10POS/NEG
B
IC1POS/NEG
IC2POS/NEG
IC3POS/NEG
XIN
XOUT
APLL2
XO
3.7-4.2GHz,
Sub-ps jitter,
Fractional-N
MAX24410 only
C
MAX24410 only
D
Processor SPI Interface
EEPROM SPI Interface
and HW Control and Status Pins
JTAG
RST_N
TEST
INTREQ
AC / GPIO1
SS / GPIO2
GPIO3
GPIO4
CS_N
SCLK
SDI
SDO
JTRST_N
JTMS
JTCLK
JTDI
JTDO
ECS_N
ESCLK
ESDI
ESDO
1
Short Form Data Sheet
MAX24405, MAX24410
1. Application Examples
Figure 1-1. Asynchronous Ethernet Clocks
XIN
25MHz
XOUT
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
Any combination of 25MHz,
125MHz, 156.25MHz and
related Ethernet frequencies
Any combination of differential or
2x single-ended signal format
Figure 1-2. Synchronous Ethernet and SDH/SONET Line Card
From dual
redundant
timing functions
19.44M,
25M, etc.
IC1P/N
IC2P/N
OC1P/N
OC2P/N
OC3P/N
OC4P/N
OC5P/N
OC6P/N
OC7P/N
OC8P/N
OC9P/N
OC10P/N
Synchronous Ethernet
Clocks: any combination
of 25M, 125M, 156.25M
and related frequencies
Any combination of differential or
2x single-ended signal format
SDH/SONET Clocks:
Nx6.48MHz to 622.08MHz
2
Short Form Data Sheet
MAX24405, MAX24410
2. Detailed Features
2.1
•
•
•
•
•
APLL Features
Two independent APLLs
Very high-resolution fractional scaling (i.e. non-integer multiplication)
Output jitter is typically 0.35 to 0.5ps RMS and can be as low as 0.24ps RMS (12kHz to 20MHz)
Telecom output frequencies include 622.08MHz for SONET/SDH and 625MHz for Synchronous Ethernet
Bypass mode for each APLL supports system testing and allows the devices to be used in fanout
applications
2.2
•
•
•
•
•
•
•
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Output Clock Features
Up to five (MAX24405) or ten (MAX24410) low-jitter output clocks
Each output can be one differential output or two CMOS/TTL outputs
Outputs easily interface with CML, LVDS, LVPECL, HSTL, SSTL, HCSL components
Each output can be any integer divisor of an APLL output clock
Supported telecom frequencies include PDH, SDH, Synchronous Ethernet, OTN
Can also produce clock frequencies for microprocessors, ASICs, FPGAs and other components
Per-output delay adjustment
Per-output enable/disable
2.3
•
•
•
•
•
General Features
SPI serial microprocessor interface
Optional automatic self-configuration at power-up from external EEPROM memory
Four general-purpose I/O pins
Register set can be write-protected
Internal compensation for local oscillator frequency error
3
Microsemi Corporation (NASDAQ: MSCC) offers a comprehensive portfolio of semiconductor
solutions for: aerospace, defense and security; enterprise and communications; and industrial
and alternative energy markets. Products include high-performance, high-reliability analog and
RF devices, mixed signal and RF integrated circuits, customizable SoCs, FPGAs, and
complete subsystems. Microsemi is headquartered in Aliso Viejo, Calif. Learn more at
www.microsemi.com
.
Microsemi Corporate Headquarters
One Enterprise, Aliso Viejo CA 92656 USA
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