CY24293
Two Outputs PCI-Express Clock Generator
Two Outputs PCI-Express Clock Generator
Features
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Functional Description
CY24293 is a two output PCI-Express clock generator device
intended for networking applications. The device takes 25 MHz
crystal or clock input and provides two pairs of differential outputs
at 25 MHz, 100 MHz, 125 MHz, or 200 MHz for HCSL signaling
standard.
The device incorporates Lexmark Spread Spectrum profile for
maximum electromagnetic interference (EMI) reduction. The
spread type and amount can be selected using select pins.
For a complete list of related documentation, click
here.
25 MHz crystal or clock input
Two sets of differential PCI-Express clocks
Pin selectable output frequencies
Supports HCSL compatible output levels
Spread Spectrum capability on all output clocks with pin
selectable spread range
16-pin TSSOP package
Operating voltage 3.3 V
Commercial, Industrial operating temperature range
Logic Block Diagram
VDDX
VDDO
XIN/EXCLKIN
(25 MHz)
XOUT
Clock Buffer/
Crystal
Oscillator
PCIE0P
PCIE0N
PLL Clock
Synthesizer
SS0
SS1
S0
S1
Control
Logic
PCIE1P
PCIE1N
I
REF
OE
GNDX
GNDO
R
REF
= 475 Ohms 1%
Cypress Semiconductor Corporation
Document Number: 001-46117 Rev. *J
•
198 Champion Court
•
San Jose
,
CA 95134-1709
•
408-943-2600
Revised June 27, 2017
CY24293
Contents
Pinouts .............................................................................. 3
Pin Definitions .................................................................. 3
Output Frequency Selection Table ................................. 4
Spread Selection Table .................................................... 4
Application Information ................................................... 5
Crystal Recommendations .......................................... 5
Crystal Loading ........................................................... 5
Calculating Load Capacitors ....................................... 5
Current Source (Iref) Reference Resistor .................... 5
Output Termination ...................................................... 6
Decoupling Capacitors ................................................ 6
PCI-Express (HCSL Compatible) Layout Guidelines .... 6
Absolute Maximum Ratings ............................................ 7
Recommended Operation Conditions ............................ 7
DC Electrical Characteristics .......................................... 7
Thermal Resistance .......................................................... 7
AC Electrical Characteristics .......................................... 8
AC Electrical Characteristics .......................................... 9
Test and Measurement Setup .......................................... 9
Ordering Information ...................................................... 10
Ordering Code Definitions ......................................... 10
Package Diagram ............................................................ 11
Acronyms ........................................................................ 12
Document Conventions ................................................. 12
Units of Measure ....................................................... 12
Document History Page ................................................. 13
Sales, Solutions, and Legal Information ...................... 15
Worldwide Sales and Design Support ....................... 15
Products .................................................................... 15
PSoC® Solutions ...................................................... 15
Cypress Developer Community ................................. 15
Technical Support ..................................................... 15
Document Number: 001-46117 Rev. *J
Page 2 of 15
CY24293
Pinouts
Figure 1. 16-pin TSSOP pinout
S0
S1
SS0
XIN/EXCLKIN
XOUT
OE
GNDX
SS1
1
2
3
4
5
6
7
8
TSSOP
16
15
14
13
12
11
10
9
VDDX
PCIE0P
PCIE0N
GNDO
VDDO
PCIE1P
PCIE1N
IREF
Pin Definitions
16-pin TSSOP
Pin Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Pin Name
S0
S1
SS0
[1]
Pin Type
Input
Input
Input
Description
Frequency select pin. Has internal weak pull-up. Refer to
Output Frequency Selection
Table on page 4.
Frequency select pin. Has internal weak pull-up. Refer to
Output Frequency Selection
Table on page 4.
Spread spectrum select pin 0. Has internal weak pull-up. Refer to
Spread Selection Table
on page 4.
Crystal or clock input. 25 MHz fundamental mode crystal or clock input.
Crystal output. 25 MHz fundamental mode crystal input. Float for clock input.
High true output enable pin. When set low, PCI-E outputs are tri-stated. Has internal weak
pull-up.
Ground
Spread spectrum select pin 1. has internal weak pull-up. Refer to
Spread Selection Table
on page 4.
Current set for all differential clock drivers. Connect 475
resistor to ground.
Differential PCI-Express complementary clock output. Tristated when disabled.
Differential PCI-Express true clock output. Tristated when disabled.
3.3 V Power supply for output driver and analog circuits.
Ground
Differential PCI-Express complementary clock output. Tristated when disabled.
Differential PCI-Express true clock output. Tristated when disabled.
3.3 V Power supply for oscillator and digital circuits.
XIN/EXCLKIN Input
XOUT
OE
GNDX
SS1
[1]
IREF
PCIE1N
PCIE1P
VDDO
[2]
GNDO
PCIE0N
PCIE0P
VDDX
[2]
Output
Input
Power
Input
Output
Output
Output
Input
Power
Output
Output
Input
Notes
1. Once powered up, state of SS1/SS0 pins should be held constant at the desired state.
2. VDDX must be supplied faster or equal to VDDO.
Document Number: 001-46117 Rev. *J
Page 3 of 15
CY24293
Output Frequency Selection Table
S1
0
0
1
1
S0
0
1
0
1
PCIE0[N,P], PCIE1[N,P]
25 MHz
100 MHz
125 MHz
200 MHz
Spread Selection Table
SS1
[3]
0
0
1
1
SS0
[3]
0
1
0
1
Spread%
No Spread
–0.5%
–0.75%
No Spread
Note
3. Once powered up, state of SS1/SS0 pins should be held constant at the desired state.
Document Number: 001-46117 Rev. *J
Page 4 of 15
CY24293
Application Information
Crystal Recommendations
CY24293 requires a parallel resonance crystal. Substituting a series resonance crystal causes the CY24293 to operate at the wrong
frequency and violate the ppm specification. For most applications, there is a 300 ppm frequency shift between series and parallel
crystals due to incorrect loading.
Table 1. Crystal Recommendations
Frequency
25.00 MHz
Cut
Parallel
Load Cap
16 pF
Eff Series Rest
(max)
30
Drive (max)
1.0 mW
Tolerance
(max)
30 ppm
Stability (max) Aging (max)
10 ppm
5 ppm/yr.
Crystal Loading
Crystal loading plays a critical role in achieving low ppm
performance. To realize low ppm performance, consider the total
capacitance the crystal sees to calculate the appropriate
capacitive loading (CL).
Figure 2
shows a typical crystal configuration using two trim
capacitors. It is important to note that the trim capacitors in series
with the crystal are not parallel. It is a common misconception
that load capacitors are in parallel with the crystal and must be
approximately equal to the load capacitance of the crystal. This
is not true.
Figure 2. Crystal Loading Example
C lock C hip
Use the following formulas to calculate the trim capacitor values
for Ce1 and Ce2:
Load capacitance (each side)
Ce
= 2 * CL – (Cs + Ci)
Total capacitance (as seen by the crystal)
CLe
=
1
(
Ce1 + Cs1 + Ci1
1
+
1
Ce2 + Cs2 + Ci2
)
CL .................................................. Crystal load capacitance
CLe ........................................ Actual loading seen by crystal
using standard value trim capacitors
Ce .................................................... External trim capacitors
Cs .............................................Stray capacitance (terraced)
C i1
Ci2
Pin
3 to 6p
Ci .......................................................... Internal capacitance
Current Source (I
REF
) Reference Resistor
If the board target trace impedance (Z) is 50
,
then for
R
REF
= 475
(1%, provides IREF of 2.32 mA. The output
current (I
OH
) is equal to 6*I
REF
. For other values of R
REF,
the
following graph can be referred. It demonstrates the relationship
of variation of IREF w.r.t. rise time /fall time (TR/TF).
Figure 3. IREF vs. TR/TF relationship (Typical)
Rise Time (single ended waveform,
measured from 0.175V to 0.525V)
240
220
200
180
160
140
120
100
420
440
460
min
typ
480
max
500
520
C s1
X1
X2
C s2
T race
2.8 pF
XTAL
Ce1
C e2
T rim
26 pF
Calculating Load Capacitors
In addition to the standard external trim capacitors, trace
capacitance and pin capacitance must also be considered to
correctly calculate crystal loading.
As mentioned in the previous section, the capacitance on each
side of the crystal is in series with the crystal. This means the
total capacitance on each side of the crystal must be twice the
specified crystal load capacitance (CL). While the capacitance
on each side of the crystal is in series with the crystal, trim
capacitors (Ce1, Ce2) must be calculated to provide equal
capacitive loading on both sides.
IREF Resistor value ()
Document Number: 001-46117 Rev. *J
Page 5 of 15
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