74LCXH162244
LOW VOLTAGE CMOS 16-BIT BUS BUFFER (3-STATE)
WITH 5V TOLERANT INPUTS AND OUTPUTS
s
s
s
s
s
s
s
s
s
s
s
s
5V TOLERANT INPUTS AND OUTPUTS
HIGH SPEED :
t
PD
= 4.4 ns (MAX.) at V
CC
= 3V
POWER DOWN PROTECTION ON INPUTS
AND OUTPUTS
SYMMETRICAL OUTPUT IMPEDANCE:
|I
OH
| = I
OL
= 12mA (MIN) at V
CC
= 3V
PCI BUS LEVELS GUARANTEED AT 12 mA
BALANCED PROPAGATION DELAYS:
t
PLH
≅
t
PHL
26Ω SERIE RESISTORS IN OUTPUTS
BUS HOLD PROVIDED ON DATA INPUT
OPERATING VOLTAGE RANGE:
V
CC
(OPR) = 2.0V to 3.6V (1.5V Data
Retention)
PIN AND FUNCTION COMPATIBLE WITH
74 SERIES H162244
LATCH-UP PERFORMANCE EXCEEDS
500mA (JESD 17)
ESD PERFORMANCE:
HBM > 2000V (MIL STD 883 method 3015);
MM > 200V
TSSOP
ORDER CODES
PACKAGE
TSSOP
TUBE
T&R
74LCXH162244TTR
PIN CONNECTION
DESCRIPTION
The 74LCX162244 is a low voltage CMOS 16 BIT
BUS BUFFER (NON-INVERTED) fabricated with
sub-micron silicon gate and double-layer metal
wiring C
2
MOS technology. It is ideal for low power
and high speed 3.3V applications; it can be
interfaced to 5V signal environment for both inputs
and outputs.
Any nG output control governs four BUS BUFF-
ERS. Output Enable input (nG) tied together gives
full 16-bit operation.
When nG is LOW, the outputs are on. When nG is
HIGH, the output are in high impedance state.
Active bus-hold circuitry is provided to hold un-
used or floating data inputs at a valid logic level.
This device is designed to be used with 3 state
memory address drivers, etc.
The device circuits is including 26Ω series resis-
tance in the outputs. These resistors permit to re-
duce line noise in high speed applications.
All inputs and outputs are equipped with protec-
tion circuits against static discharge, giving them
2KV ESD immunity and transient excess voltage.
February 2003
1/10
74LCXH162244
ABSOLUTE MAXIMUM RATINGS
Symbol
V
CC
V
I
V
O
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
T
L
Supply Voltage
DC Input Voltage
DC Output Voltage (OFF State)
DC Output Voltage (High or Low State) (note 1)
DC Input Diode Current
DC Output Diode Current (note 2)
DC Output Current
DC Supply Current per Supply Pin
DC Ground Current per Supply Pin
Storage Temperature
Lead Temperature (10 sec)
Parameter
Value
-0.5 to +7.0
-0.5 to +7.0
-0.5 to +7.0
-0.5 to V
CC
+ 0.5
- 50
- 50
±
50
±
100
±
100
-65 to +150
300
Unit
V
V
V
V
mA
mA
mA
mA
mA
°C
°C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is
not implied
1) I
O
absolute maximum rating must be observed
2) V
O
< GND
RECOMMENDED OPERATING CONDITIONS
Symbol
V
CC
V
I
V
O
V
O
I
OH
, I
OL
I
OH
, I
OL
T
op
dt/dv
Supply Voltage (note 1)
Input Voltage
Output Voltage (OFF State)
Output Voltage (High or Low State)
High or Low Level Output Current (V
CC
= 3.0 to 3.6V)
High or Low Level Output Current (V
CC
= 2.7V )
Operating Temperature
Input Rise and Fall Time (note 2)
Parameter
Value
2.0 to 3.6
0 to 5.5
0 to 5.5
0 to V
CC
±
12
±
8
-55 to 125
0 to 10
Unit
V
V
V
V
mA
mA
°C
ns/V
1) Truth Table guaranteed: 1.5V to 3.6V
2) V
IN
from 0.8V to 2V at V
CC
= 3.0V
3/10
74LCXH162244
AC ELECTRICAL CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
2.7
3.0 to 3.6
2.7
3.0 to 3.6
2.7
3.0 to 3.6
3.0 to 3.6
C
L
(pF)
50
50
50
50
R
L
(Ω)
500
500
500
500
t
s
=
t
r
(ns)
2.5
2.5
2.5
2.5
-40 to 85 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
5.6
4.4
6.3
5.9
6.3
5.9
1.0
Value
-55 to 125 °C
Min.
1.5
1.5
1.5
1.5
1.5
1.5
Max.
6.5
5.1
7.2
6.8
7.2
6.8
1.0
ns
ns
ns
ns
Unit
t
PLH
t
PHL
t
PZL
t
PZH
t
PLZ
t
PHZ
t
OSLH
t
OSHL
Propagation Delay
Time
Output Enable Time
Output Disable Time
Output To Output
Skew Time (note1,
2)
1) Skew is defined as the absolute value of the difference between the actual propagation delay for any two outputs of the same device switch-
ing in the same direction, either HIGH or LOW (t
OSLH
= | t
PLHm
- t
PLHn
|, t
OSHL
= | t
PHLm
- t
PHLn
|)
2) Parameter guaranteed by design
CAPACITIVE CHARACTERISTICS
Test Condition
Symbol
Parameter
V
CC
(V)
Value
T
A
= 25 °C
Min.
Typ.
4
10
3.3
f
IN
= 10MHz
V
IN
= 0 or V
CC
50
Max.
pF
pF
pF
Unit
C
IN
C
OUT
C
PD
Input Capacitance
Output Capacitance
Power Dissipation Capacitance
(note 1)
1) C
PD
is defined as the value of the IC’s internal equivalent capacitance which is calculated from the operating current consumption without
load. (Refer to Test Circuit). Average operating current can be obtained by the following equation. I
CC(opr)
= C
PD
x V
CC
x f
IN
+ I
CC
/16 (per
circuit)
5/10
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