74LVC623A-Q100
Octal transceiver with dual enable; 3-state
Rev. 1 — 17 April 2013
Product data sheet
1. General description
The 74LVC623A-Q100 is an octal transceiver featuring non-inverting 3-state bus
compatible outputs in both send and receive directions. This octal bus transceiver is
designed for asynchronous two-way communication between data buses.
The control function implementation allows maximum flexibility in timing. This device
allows data transmission from the An bus to the Bn bus or from the Bn bus to the An bus.
The data flow direction depends on the logic levels at the enable inputs (pins OEAB and
OEBA). The enable inputs can be used to disable the device so that the buses are
effectively isolated. The dual enable function configuration gives this transceiver the
capability to store data by simultaneous enabling of pins OEAB and OEBA. Each output
reinforces its input in this transceiver configuration. Thus, when both control inputs are
enabled and all other data sources to the two sets of the bus lines are at high-impedance
OFF-state, both sets of the bus lines remain at their last states. The 8-bit codes on the two
sets of buses are identical.
Inputs can be driven from either 3.3 V or 5 V devices. When disabled, up to 5.5 V can be
applied to the outputs. These features allow the use of these devices as translators in
mixed 3.3 V or 5 V applications.
This product has been qualified to the Automotive Electronics Council (AEC) standard
Q100 (Grade 1) and is suitable for use in automotive applications.
2. Features and benefits
Automotive product qualification in accordance with AEC-Q100 (Grade 1)
Specified from
40 C
to +85
C
and from
40 C
to +125
C
5 V tolerant inputs and outputs for interfacing with 5 V logic
Wide supply voltage range from 1.2 V to 3.6 V
CMOS low power consumption
Direct interface with TTL levels
High-impedance when V
CC
= 0 V
Complies with JEDEC standard:
JESD8-7A (1.65 V to 1.95 V)
JESD8-5A (2.3 V to 2.7 V)
JESD8-C/JESD36 (2.7 V to 3.6 V)
ESD protection:
MIL-STD-883, method 3015 exceeds 2000 V
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V (C = 200 pF, R = 0
)
NXP Semiconductors
74LVC623A-Q100
Octal transceiver with dual enable; 3-state
3. Ordering information
Table 1.
Ordering information
Package
Temperature range
74LVC623AD-Q100
74LVC623ADB-Q100
74LVC623APW-Q100
40 C
to +125
C
40 C
to +125
C
40 C
to +125
C
Name
SO20
SSOP20
TSSOP20
Description
plastic small outline package; 20 leads;
body width 7.5 mm
Version
SOT163-1
Type number
plastic shrink small outline package; 20 leads; SOT339-1
body width 5.3 mm
plastic thin shrink small outline package;
20 leads; body width 4.4 mm
SOT360-1
4. Functional diagram
19
1
1
2
3
4
5
6
7
8
9
EN1
EN2
OEAB
A0
A1
A2
A3
A4
A5
A6
A7
OEBA
19
B0
B1
B2
B3
B4
B5
B6
B7
18
17
16
15
4
14
13
12
11
5
6
7
8
9
2
1
2
18
3
17
16
15
14
13
12
11
001aaa844
001aaa833
Fig 1.
Logic symbol
Fig 2.
IEC logic symbol
74LVC623A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
2 of 18
NXP Semiconductors
74LVC623A-Q100
Octal transceiver with dual enable; 3-state
5. Pinning information
5.1 Pinning
/9&$4
2($%
$
$
$
$
$
$
$
$
9
&&
2(%$
%
%
%
%
%
%
%
%
DDD
*1'
Fig 4.
Pin configuration SO20 and (T)SSOP20
5.2 Pin description
Table 2.
Pin
1
19
A[0:7]
B[0:7]
10
20
Pin description
Symbol
OEAB
OEBA
2, 3, 4, 5, 6, 7, 8, 9
18, 17, 16, 15, 14, 13, 12, 11
GND
V
CC
Description
output enable input
output enable input (active LOW)
data input or output
data output or input
ground (0 V)
supply voltage
74LVC623A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
4 of 18
NXP Semiconductors
74LVC623A-Q100
Octal transceiver with dual enable; 3-state
6. Functional description
Table 3.
Input
OEAB
L
H
L
H
OEBA
L
H
H
L
Function table
[1]
Input or output
An
An = Bn
input
Z
An = Bn
input
[1]
H = HIGH voltage level; L = LOW voltage level; Z = high-impedance OFF-state
Bn
input
Bn = An
Z
input
Bn = An
7. Limiting values
Table 4.
Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol
V
CC
V
I
V
O
I
IK
I
OK
I
O
I
CC
I
GND
T
stg
P
tot
[1]
[2]
[3]
Parameter
supply voltage
input voltage
output voltage
input clamping current
output clamping current
output current
supply current
ground current
storage temperature
total power dissipation
Conditions
[1]
Min
0.5
0.5
0.5
0.5
50
-
-
-
100
65
Max
+6.5
+6.5
V
CC
+ 0.5
+6.5
-
50
50
100
-
150
500
Unit
V
V
V
V
mA
mA
mA
mA
mA
C
mW
HIGH or LOW state
3-state
V
I
< 0 V
V
O
> V
CC
or V
O
< 0 V
V
O
= 0 V to V
CC
[2]
[2]
T
amb
=
40C
to +125
C
[3]
-
The minimum input voltage ratings may be exceeded if the input current ratings are observed.
The output voltage ratings may be exceeded if the output current ratings are observed.
For SO20 package: above 70
C
P
tot
derates linearly with 8 mW/K.
For (T)SSOP20 packages: above 60
C
P
tot
derates linearly with 5.5 mW/K.
74LVC623A_Q100
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 1 — 17 April 2013
5 of 18
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