S i531 9
A
N Y
-F
REQU EN C Y
P
R E C I S I O N
C
LO C K
M
U LTI PL IE R
/J
IT TER
A
TT EN UA T OR
Features
Generates any frequency from 2 kHz to 945 MHz and
select frequencies to 1.4 GHz from an input frequency of
2 kHz to 710 MHz
Ultra-low jitter clock output with jitter generation as low as
0.3 ps rms (50 kHz–80 MHz)
Integrated loop filter with selectable loop bandwidth
(60 Hz to 8.4 kHz)
Meets OC-192 GR-253-CORE jitter specifications
Clock or crystal input with manual clock selection
Selectable clock output signal format
(LVPECL, LVDS, CML, CMOS)
Support for ITU G.709 and custom OTN FEC ratios (e.g.
255/238, 255/237, 255/236)
Supports various frequency translations for Synchronous
Ethernet
LOL, LOS alarm outputs
I
2
C or SPI programmable
On-chip voltage regulator for 1.8 V ±5%, 2.5 V ±10% or
3.3 V ±10% operation
Small size: 6 x 6 mm 36-lead QFN
Pb-free, ROHS compliant
Applications
10G/40G/100G OTN line cards
SONET/SDH OC-48/STM-16 and OC-192/STM-64
line cards
GbE/10GbE, 1/2/4/8/10GFC line cards
ITU G.709 and custom FEC line cards
Synchronous Ethernet
Optical modules
Wireless basestations
Data converter clocking
DSLAM/MSANs
Test and measurement
Broadcast video
Discrete PLL replacement
Description
The Si5319 is a jitter-attenuating precision M/N clock multiplier for applications requiring sub 1 ps jitter performance. The
Si5319 accepts one clock input ranging from 2 kHz to 710 MHz and generates one clock output ranging from 2 kHz to 945 MHz
and select frequencies to 1.4 GHz. The Si5319 can also use its crystal oscillator as a clock source for free-running clock
generation. The device provides virtually any frequency translation combination across this operating range. The Si5319 input
clock frequency and clock multiplication ratio are programmable through an I
2
C or SPI interface. The Si5319 is based on Silicon
Laboratories' third-generation DSPLL
®
technology, which provides any-frequency synthesis and jitter attenuation in a highly
integrated PLL solution that eliminates the need for external VCXO and loop filter components. The DSPLL loop bandwidth is
digitally programmable, providing jitter performance optimization at the application level. Operating from a single 1.8, 2.5, or
3.3 V supply, the Si5319 is ideal for providing clock multiplication and jitter attenuation in high performance timing applications.
Rev. 1.0 12/10
Copyright © 2010 by Silicon Laboratories
Si5319
Si5319
T
A B L E
Section
OF
C
ONTENTS
Page
1. Electrical Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4
2. Typical Phase Noise Plots . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
2.1. Example: SONET OC-192 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.1. External Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
3.2. Further Documentation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4. Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
5. Pin Descriptions: Si5319 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40
6. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43
7. Package Outline: 36-Pin QFN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44
8. Recommended PCB Layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45
9. Si5319 Device Top Mark . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47
Document Change List . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .48
Contact Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50
Rev. 1.0
3
Si5319
1. Electrical Specifications
Table 1. Recommended Operating Conditions
Parameter
Ambient Temperature
Supply Voltage during
Normal Operation
Symbol
T
A
V
DD
3.3 V Nominal
2.5 V Nominal
1.8 V Nominal
Test Condition
Min
-40
2.97
2.25
1.71
Typ
25
3.3
2.5
1.8
Max
85
3.63
2.75
1.89
Unit
°C
V
V
V
Note:
All minimum and maximum specifications are guaranteed and apply across the recommended operating conditions.
Typical values apply at nominal supply voltages and an operating temperature of 25 ºC unless otherwise stated.
Figure 1.
Differential Voltage Characteristics
Figure 2.
Rise/Fall Time Characteristics
4
Rev. 1.0
Si5319
Table 2. DC Characteristics
(V
DD
= 1.8 ± 5%, 2.5 ±10%, or 3.3 V ±10%, T
A
= –40 to 85 °C)
Parameter
Supply Current
1
Symbol
I
DD
Test Condition
LVPECL Format
622.08 MHz Out
CMOS Format
19.44 MHz Out
Disable Mode
Min
—
—
—
Typ
217
194
165
Max
243
220
—
Unit
mA
mA
mA
CKIN Input Pin
2
Input Common Mode
Voltage (Input Thresh-
old Voltage)
V
ICM
1.8 V ± 5%
2.5 V ± 10%
3.3 V ± 10%
Input Resistance
Single-Ended Input
Voltage Swing
(See Absolute Specs)
CKN
RIN
V
ISE
Single-ended
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
V
ID
f
CKIN
< 212.5 MHz
See Figure 1.
f
CKIN
> 212.5 MHz
See Figure 1.
0.9
1
1.1
20
0.2
0.25
0.2
0.25
—
—
—
40
—
—
—
—
1.4
1.7
1.95
60
—
—
—
—
V
V
V
kΩ
V
PP
V
PP
V
PP
V
PP
Differential Input
Voltage Swing
(See Absolute Specs)
Output Clock (CKOUT)
3
Common Mode
Differential Output
Swing
Single Ended Output
Swing
Differential Output
Voltage
CKO
VCM
CKO
VD
CKO
VSE
CKO
VD
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
LVPECL 100
load
line-to-line
CML 100
load line-to-
line
V
DD
–1.42
1.1
0.5
350
—
—
—
425
V
DD
–1.25
1.9
0.93
500
V
V
PP
V
PP
mV
PP
Notes:
1.
Current draw is independent of supply voltage.
2.
No under- or overshoot is allowed.
3.
LVPECL outputs require nominal V
DD
≥
2.5 V.
4.
This is the amount of leakage that the 3-level inputs can tolerate from an external driver. See Si53xx Family
Reference Manual for more details.
5.
LVPECL, CML, LVDS and low-swing LVDS measured with Fo = 622.08 MHz.
Rev. 1.0
5
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