VCXO-to-LVCMOS/ LVTTL Output
Datasheet
8101925
General Description
The 8101925 is a high performance, low jitter/low phase noise
VCXO from IDT. The 8101925 works in conjunction with a 25MHz
pullable crystal to generate an LVCMOS/LVTTL output clock of
25MHz from an input clock of 5MHz or 19.44MHz. The output range
is ±100ppm around the nominal crystal frequency. The device is
packaged in a small 16 TSSOP package and is ideal for use on
space constrained boards.
Features
•
•
•
•
•
•
•
•
•
•
One single-ended LVCMOS or LVTTL output
One single-ended clock accepts the following input types:
LVCMOS, LVTTL
Output frequency: 25MHz
Accepts 5MHz or 19.44MHz with auto input frequency detect
Absolute pull range (APR): ±100ppm
RMS phase jitter. (12kHz – 5MHz): 0.4ps (typical)
Full 3.3V supply, or 3.3V core/2.5V output supply
-40°C to 85°C ambient operating temperature
Available in lead-free (RoHS 6) package
For functional replacement part use 810252
Block Diagram
Loop
Filter
Pin Assignment
nc
GND
Q
V
DDO
nc
nc
V
DDA
V
DD
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
DD
CLK
GND
LF1
LF0
XTAL_IN
XTAL_OUT
GND
(÷125 or ÷486)
Phase
Detector
XTAL_IN
25MHz
XTAL_OUT
LF0
LF1
8101925
VCXO
Charge
Pump
CLK
Pulldown
5MHz or 19.44MHz
Frequency auto detect
Pre-Divider
Q
25MHz
VCXO Feedback Divider
÷625
16-Lead TSSOP
4.4mm x 5.0mm x 0.925mm
package body
G Package
Top View
VCXO Jitter Attenuation PLL
©2016 Integrated Device Technology, Inc.
1
Revision B, November 7, 2016
8101925 Datasheet
Table 1. Pin Descriptions
Number
1, 5, 6
2, 9, 14
3
4
7
8, 16
10,
11
12
Name
nc
GND
Q
V
DDO
V
DDA
V
DD
XTAL_OUT,
XTAL_IN
LF0
Unused
Power
Output
Power
Power
Power
Input
Analog
Input/
Output
Analog
Input/
Output
Input
Pulldown
Type
Description
No connect.
Power supply ground.
Single-ended clock output. LVCMOS/ LVTTL interface levels.
Output power supply pin.
Analog supply pin.
Core power supply pins.
VCXO crystal oscillator interface. XTAL_IN is the input. XTAL_OUT is the output.
Output to external loop filter. Charge pump output.
13
LF1
Input from external loop filter. VCXO control voltage input.
Single-ended clock input with auto frequency detect. LVCMOS/LVTTL interface
levels.
15
CLK
NOTE:
Pulldown
refers to an internal input resistor. See Table 2,
Pin Characteristics,
for typical values.
Table 2. Pin Characteristics
Symbol
C
IN
Parameter
Input Capacitance
Test Conditions
Minimum
Typical
4
51
V
DDO
= 3.3V±5%
V
DDO
= 2.5V±5%
17
20
Maximum
Units
pF
k
R
PULLDOWN
Input Pulldown Resistor
R
OUT
Output Impedance
©2016 Integrated Device Technology, Inc.
2
Revision B, November 7, 2016
8101925 Datasheet
Absolute Maximum Ratings
NOTE: Stresses beyond those listed under
Absolute Maximum Ratings
may cause permanent damage to the device.
These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond
those listed in the
DC Characteristics or AC Characteristics
is not implied. Exposure to absolute maximum rating conditions for
extended periods may affect product reliability.
Item
Supply Voltage, V
DD
Inputs, V
I
Outputs, V
O
Package Thermal Impedance,
JA
Storage Temperature, T
STG
Rating
4.6V
-0.5V to V
DD
+ 0.5V
-0.5V to V
DD
+ 0.5V
81.2C/W (0 mps)
-65C to 150C
DC Electrical Characteristics
Table 3A. Power Supply DC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
3.135
V
DD
– 0.05
3.135
Typical
3.3
3.3
3.3
Maximum
3.465
V
DD
3.465
83
5
1
Units
V
V
V
mA
mA
mA
Table 3B. Power Supply DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
DD
V
DDA
V
DDO
I
DD
I
DDA
I
DDO
Parameter
Core Supply Voltage
Analog Supply Voltage
Output Supply Voltage
Power Supply Current
Analog Supply Current
Output Supply Current
Test Conditions
Minimum
2.375
V
DD
– 0.05
2.375
Typical
2.5
2.5
2.5
Maximum
2.625
V
DD
2.625
81
5
1
Units
V
V
V
mA
mA
mA
©2016 Integrated Device Technology, Inc.
3
Revision B, November 7, 2016
8101925 Datasheet
Table 3C. LVCMOS/LVTTL DC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 3.3V ± 5% or 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
V
IH
Parameter
Input
High Voltage
Input
Low Voltage
VCXO Control Voltage
Input High Current
Input Low Current
Output High Voltage
V
DD
= V
IN
= 3.465V or 2.625V
V
DD
= 3.465V or 2.625V, V
IN
= 0V
V
DDO
= 3.3V ± 5%, I
OH
= -12mA
V
DDO
= 2.5V ± 5%, I
OH
= -12mA
Output Low Voltage
V
DDO
= 3.3V or 2.5V ± 5%,
I
OL
= 12mA
-5
2.6
1.8
0.5
Test Conditions
V
DD
= 3.465V
V
DD
= 2.625V
V
DD
= 3.465V
V
DD
= 2.625V
Minimum
2
1.7
-0.3
-0.3
0
Typical
Maximum
V
DD
+ 0.3
V
DD
+ 0.3
0.8
0.7
V
DD
150
Units
V
V
V
V
V
µA
µA
V
V
V
V
IL
V
LF1
I
IH
I
IL
V
OH
V
OL
AC Electrical Characteristics
Table 4A. AC Characteristics,
V
DD
= V
DDO
= 3.3V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
f
IN
tjit()
t
R
/ t
F
odc
Parameter
Output Frequency
Input Frequency
RMS Phase Jitter (Random);
NOTE 1
Output Rise/Fall Time
Output Duty Cycle
f
OUT
= 25MHz, Integration Range:
12kHz – 5MHz
20% to 80%
650
40
0.4
1050
60
Test Conditions
Minimum
Typical
25
5
19.44
Maximum
Units
MHz
MHz
MHz
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when the device
is mounted in a test socket with maintained transverse airflow greater than 500 lfpm. The device will meet specifications after thermal
equilibrium has been reached under these conditions.
NOTE: Characterized using a 48Hz bandwidth filter.
NOTE 1: Refer to the Phase Noise Plot.
Table 4B. AC Characteristics,
V
DD
= 3.3V ± 5%, V
DDO
= 2.5V ± 5%, T
A
= -40°C to 85°C
Symbol
f
OUT
f
IN
tjit()
t
R
/ t
F
odc
Parameter
Output Frequency
Input Frequency
RMS Phase Jitter (Random);
Output Rise/Fall Time
Output Duty Cycle
f
OUT
= 25MHz, Integration Range:
12kHz – 5MHz
20% to 80%
900
40
0.4
1600
60
Test Conditions
Minimum
Typical
25
5
19.44
Maximum
Units
MHz
MHz
MHz
ps
ps
%
NOTE: Electrical parameters are guaranteed over the specified ambient operating temperature range, which is established when device is
mounted in a test socket with maintained transverse airflow greater than 500 lfpm. Device will meet specifications after thermal equilibrium has
been reached under these conditions.
NOTE: Characterized using a 48Hz bandwidth filter.
©2016 Integrated Device Technology, Inc.
4
Revision B, November 7, 2016
8101925 Datasheet
Typical Phase Noise at 25MHz
25MHz
RMS Phase Jitter (Random)
12kHz to 5MHz = 0.4ps (typical)
Noise Power dBc
Hz
Offset Frequency (Hz)
©2016 Integrated Device Technology, Inc.
5
Revision B, November 7, 2016
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
