NBSG53A
2.5 V/3.3 V SiGe Selectable
Differential Clock and Data
D Flip-Flop/Clock Divider
with Reset and OLS*
The NBSG53A is a multi-function differential D flip-flop (DFF) or
fixed divide by two (DIV/2) clock generator. This is a part of the
GigaCommt family of high performance Silicon Germanium
products. A strappable control pin is provided to select between the
two functions. The device is housed in a low profile 4x4 mm 16-pin
Flip-Chip BGA (FCBGA) or a 3x3 mm 16 pin QFN package.
The NBSG53A is a device with data, clock, OLS*, reset, and select
inputs. Differential inputs incorporate internal 50
W
termination
resistors and accept NECL (Negative ECL), PECL (Positive ECL),
LVCMOS/LVTTL, CML, or LVDS. The OLS* input is used to
program the peak-to-peak output amplitude between 0 and 800 mV
in five discrete steps. The RESET and SELECT inputs are
single-ended and can be driven with either LVECL or
LVCMOS/LVTTL input levels.
Data is transferred to the outputs on the positive edge of the clock.
The differential clock inputs of the NBSG53A allow the device to also
be used as a negative edge triggered device.
Features
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1
QFN−16
MN SUFFIX
CASE 485G
MARKING DIAGRAM*
•
Maximum Input Clock Frequency (DFF) > 8 GHz Typical
(See Figures 3, 5, 7, 9, and 10)
•
Maximum Input Clock Frequency (DIV/2) > 10 GHz Typical
(See Figures 4, 6, 8, 9, and 10)
•
210 ps Typical Propagation Delay (OLS = FLOAT)
A
L
Y
W
G
(Note: Microdot may be in either location)
*For additional marking information, refer to
Application Note AND8002/D.
•
•
•
•
45 ps Typical Rise and Fall Times (OLS = FLOAT)
DIV/2 Mode (Active with Select Low)
DFF Mode (Active with Select High)
ORDERING INFORMATION
See detailed ordering and shipping information in the package
dimensions section on page 16 of this data sheet.
Selectable Swing PECL Output with Operating Range: V
CC
= 2.375 V
to 3.465 V with V
EE
= 0 V
•
Selectable Swing NECL Output with NECL Inputs with
Operating Range: V
CC
= 0 V with V
EE
= −2.375 V to −3.465 V
•
Selectable Output Level (0 V, 200 mV, 400 mV, 600 mV, or 800 mV
Peak-to-Peak Output)
•
50
W
Internal Input Termination Resistors on all Differential Inputs
•
These are Pb-Free Devices
*Output Level Select
©
Semiconductor Components Industries, LLC, 2014
1
June, 2014 − Rev. 15
ÇÇÇ
ÇÇÇ
1
16
SG
53A
ALYWG
G
= Assembly Location
= Wafer Lot
= Year
= Work Week
= Pb−Free Package
Publication Order Number:
NBSG53A/D
NBSG53A
V
CC
16
VTCLK
CLK
CLK
VTCLK
R
15
SEL OLS
14
13
Exposed Pad
(EP)
12
11
NBSG53A
3
4
10
9
Q
V
CC
V
EE
Q
1
2
5
VTD
6
D
7
D
8
VTD
Figure 1. QFN−16 Pinout
(Top View)
Table 1. PIN DESCRIPTION
Pin
1
2
Name
VTCLK
CLK
I/O
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
ECL, CML,
LVCMOS, LVDS,
LVTTL Input
−
−
RSECL Output
RSECL Output
−
Input
LVECL, LVCMOS,
LVTTL Input
LVECL, LVCMOS,
LVTTL Input
Description
Internal 50
W
Termination Pin. See Table 4.
Inverted Differential Input.
3
CLK
Noninverted Differential Input.
4
5
6
VTCLK
VTD
D
Internal 50
W
Termination Pin. See Table 4.
Internal 50
W
termination pin. See Table 4.
Inverted Differential Input.
7
D
Noninverted Differential Input.
8
9,16
10
11
12
13
14
15
−
VTD
V
CC
Q
Q
V
EE
OLS*
SEL
R
EP
Internal 50
W
Termination Pin. See Table 4.
Positive Supply Voltage
NonInverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
− 2 V.
Inverted Differential Output. Typically Terminated with 50
W
Resistor to
V
TT
= V
CC
− 2 V.
Negative Supply Voltage
Input Pin for the Output Level Select (OLS). See Table 2.
Select Logic Input. Internal 75 kW to V
EE
.
Reset D Flip-Flop. Internal 75 kW to V
EE
.
The Exposed Pad (EP) on the QFN−16 package bottom is thermally connected to the
die for improved heat transfer out of package. The exposed pad must be attached to
a heat-sinking conduit. The pad is not electrically connected to the die but may be
electrically and thermally connected to V
EE
on the PC board.
1. All V
CC
and V
EE
pins must be externally connected to Power Supply to guarantee proper operation. The thermally exposed pad (EP) on
package bottom (see case drawing) must be attached to a heat-sinking conduit.
2. In the differential configuration when the input termination pins (VTD, VTD, VTCLK, VTCLK) are connected to a common termination voltage,
and if no signal is applied then the device will be susceptible to self-oscillation.
3. When an output level of 400 mV is desired and V
CC
− V
EE
> 3.0 V, 2 kW resistor should be connected from OLS pin to V
EE
.
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2
NBSG53A
V
CC
OLS
VTD
50
W
D
D
50
W
VTD
2
2
D
Flip−Flop
(DFF)
R
2
2
VTCLK
50
W
CLK
CLK
50
W
VTCLK
R
SEL
75 kW
75 kW
2
R
Q
D
Flip−Flop
(DIV/2)
Q
2
1
0
2
Q
Q
V
EE
Figure 2. Simplified Logic Diagram
Table 2. OUTPUT LEVEL SELECT (OLS)
OLS
V
CC
V
CC
− 0.4 V
V
CC
− 0.8 V
V
CC
− 1.2 V
V
EE
(Note 4)
Float
Q/Q VPP
800 mV
200 mV
600 mV
0
400 mV
600 mV
OLS Sensitivity
OLS − 75 mV
OLS
$
150 mV
OLS
$
100 mV
OLS
$
75 mV
OLS + 100 mV
N/A
Table 3. TRUTH TABLE
R
H
L
L
L
SEL
x
H
H
L
D
x
L
H
x
CLK
x
Z
Z
Z
Q
L
L
H
Q
Function
Reset
DFF
DFF
DIV/2
Z = LOW to HIGH Transition
4. When an output level of 400 mV is desired and
V
CC
− V
EE
> 3.0 V, 2.0 kW resistor should be connected from
OLS to V
EE
.
Table 4. INTERFACING OPTIONS
INTERFACING OPTIONS
CML
LVDS
AC−COUPLED
RSECL, PECL, NECL
LVTTL, LVCMOS
CONNECTIONS
Connect VTCLK, VTD and VTCLK, VTD to V
CC
Connect VTCLK, VTD and VTCLK, VTD Together
Bias VTCLK, VTD and VTCLK, VTD Inputs within Common Mode Range (V
IHCMR
)
Standard ECL Termination Techniques
An External Voltage (V
th
) should be Applied to the Unused Complementary Differential Input. Nominal V
th
is
1.5 V for LVTTL and V
CC
/2 for LVCMOS Inputs. This Voltage must be within the V
th
Specification.
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NBSG53A
Table 5. ATTRIBUTES
Characteristics
Positive Operating Voltage Range for V
CC
(V
EE
= 0 V)
Negative Operating Voltage Range for V
EE
(V
CC
= 0 V)
Internal Input Pulldown Resistor (R, SEL)
ESD Protection
Human Body Model
Machine Model
Charged Device Model
Value
2.375 V to 3.465 V
−2.375 V to −3.465 V
75 kW
> 1.5 kV
> 50 V
> 4 kV
Level 1
UL 94 V−0 @ 0.125 in
28 to 34
482
Moisture Sensitivity (Note 5)
Flammability Rating
Oxygen Index
Transistor Count
Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test
5. For additional information, refer to Application Note AND8003/D.
Table 6. MAXIMUM RATINGS
Symbol
V
CC
V
EE
V
I
V
INPP
I
IN
I
OUT
T
A
T
stg
q
JA
q
JC
T
sol
Parameter
Positive Power Supply
Negative Power Supply
Positive Input
Negative Input
Differential Input Voltage
|D − D|
Condition 1
V
EE
= 0 V
V
CC
= 0 V
V
EE
= 0 V
V
CC
= 0 V
V
CC
− V
EE
≥
2.8 V
V
CC
− V
EE
< 2.8 V
Static
Surge
Continuous
Surge
V
I
≤
V
CC
V
I
≥
V
EE
Condition 2
Rating
3.6
−3.6
3.6
−3.6
2.8
|V
CC
− V
EE
|
45
80
25
50
−40 to +85
−65 to +150
0 lfpm
500 lfpm
2S2P (Note 6)
< 3 sec @ 260°C
41.6
35.2
4.0
265
Units
V
V
V
V
mA
mA
°C
°C
°C/W
°C/W
°C
Input Current Through R
T
(50
W
Resistor)
Output Current
Operating Temperature Range
Storage Temperature Range
Thermal Resistance (Junction-to-Ambient)
(Note 6)
Thermal Resistance (Junction-to-Case)
Wave Solder
Pb-Free
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be affected.
6. JEDEC standard multilayer board − 2S2P (2 signal, 2 power) with 8 filled thermal vias under exposed pad.
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NBSG53A
Table 7. DC CHARACTERISTICS, INPUT WITH PECL OUTPUT
(V
CC
= 2.5 V; V
EE
= 0 V) (Note 7)
−40°C
Symbol
Characteristic
Min
Typ
Max
Min
25°C
Typ
Max
Min
85°C
Typ
Max
Unit
POWER SUPPLY CURRENT
I
EE
V
OH
V
OL
Negative Power Supply Current
33
45
57
33
45
57
33
45
57
mA
PECL OUTPUTS
(Note 8)
Output HIGH Voltage
Output LOW Voltage
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
(OLS = V
EE
)
V
OUTPP
Output Voltage Amplitude
(OLS = V
CC
)
(OLS = V
CC
− 0.4 V)
(OLS = V
CC
− 0.8 V, OLS = FLOAT)
(OLS = V
CC
− 1.2 V)
(OLS = V
EE
)
Input HIGH
Voltage
Input LOW
Voltage
CLK, invCLK, D, D
R, SEL
CLK, invCLK, D, D
R, SEL
V
th
V
ISE
Input Threshold Voltage Range
(Note 10)
Single-Ended Input Voltage
(V
IH
– V
IL
)
555
1235
775
1455
1005
670
125
510
0
325
705
1295
895
1505
1095
800
215
615
5
415
855
1385
1015
1585
1215
595
1270
810
1490
1040
660
120
505
0
320
745
1330
930
1540
1130
795
210
610
0
410
895
1420
1050
1620
1250
625
1295
840
1510
1065
655
120
500
0
320
775
1355
960
1560
1155
790
210
605
0
410
925
1445
1080
1640
1275
mV
1460
1510
1560
1490
1540
1590
1515
1565
1615
mV
mV
DIFFERENTIAL CLOCK INPUTS DRIVEN SINGLE-ENDED
(Figures 13 & 15) (Note 9)
V
IH
V
IL
1200
1290
0
0
1125
150
V
CC
V
CC
V
IH
−
150
890
V
CC
–
75
2600
1200
1355
0
0
1125
150
V
CC
V
CC
V
IH
−
150
955
V
CC
–
75
2600
1200
1415
0
0
1125
150
V
CC
V
CC
V
IH
−
150
1015
V
CC
–
75
260
mV
mV
mV
mV
DIFFERENTIAL INPUTS DRIVEN DIFFERENTIALLY
(Figures 14 & 16) (Note 11)
V
IHD
V
ILD
V
ID
V
IHCMR
I
IH
I
IL
Differential Input HIGH Voltage
Differential Input LOW Voltage
Differential Input Voltage
(V
IHD
– V
ILD
)
Input HIGH Voltage Common Mode
Range (Note 12) (Figure 17)
Input HIGH Current (@V
IH
) R, SEL
CLK, inv_CLK, D, inv_D
Input LOW Current (@V
IL
)
R, SEL
CLK, inv_CLK, D, inv_D
1200
0
75
1200
35
5
20
5
V
CC
V
IHD
−
75
2600
2500
100
50
100
50
1200
0
75
1200
35
5
20
5
V
CC
V
IHD
−
75
2600
2500
100
50
100
50
1200
0
75
1200
35
5
20
5
V
CC
V
IHD
−
75
2600
2500
100
50
100
50
mV
mV
mV
mV
mA
mA
TERMINATION RESISTORS
R
TIN
Internal Input Termination Resistor
45
50
55
45
50
55
45
50
55
W
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product
performance may not be indicated by the Electrical Characteristics if operated under different conditions.
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit
board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared
operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit
values are applied individually under normal operating conditions and not valid simultaneously.
7. Input and output parameters vary 1:1 with V
CC
.
8. All outputs loaded with 50
W
to V
CC
− 2.0 V.
9. V
th
, V
IH
, V
IL,
and V
ISE
parameters must be complied with simultaneously.
10. V
th
is applied to the complementary input when operating in single-ended mode. V
th
= (V
IH
− V
IL
) / 2.
11. V
IHD
, V
ILD,
V
ID
and V
IHCMR
parameters must be complied with simultaneously.
12. V
IHCMR
min varies 1:1 with V
EE
, V
IHCMR
max varies 1:1 with V
CC
. The V
IHCMR
range is referenced to the most positive side of the differential
input signal.
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