EVALUATION KIT AVAILABLE
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
General Description
The MAX14920/MAX14921 battery measurement analog
front-end devices accurately sample cell voltages and
provide level shifting for primary/secondary battery packs
up to 16 cells/+65V (max). The MAX14920 monitors up
to 12 cells, while the MAX14921 monitors up to 16 cells.
Both devices simultaneously sample all cell voltages,
allowing accurate state-of-charge and source-resistance
determination. All cell voltages are level shifted to ground
reference with unity gain, simplifying external ADC data
conversion.
The devices have a low-noise, low-offset amplifier that
buffers differential voltages of up to +5V, allowing moni-
toring of all common lithium-ion (Li+) cell technologies.
The resulting cell voltage error is
Q0.5mV.
The devices’ high accuracy make them ideal for monitoring
cell chemistries with very flat discharge curves, such as
lithium-metal phosphate.
Passive-cell balancing is supported by external FET
drivers. Integrated diagnostics in the devices allow
open-wire detection and undervoltage/overvoltage
alarms. The devices are controlled by a daisy-chainable
SPI interface.
The MAX14920 is available in a 64-pin (10mm x 10mm)
TQFP package with an exposed pad. The MAX14921 is
available in an 80-pin (12mm x 12mm) TQFP package.
Both devices are specified over the -40°C to +85°C
extended temperature range.
Benefits and Features
S
High Accuracy
±0.5mV (max) Cell Voltage
Simultaneous Cell Voltage Sampling
Self-Calibration
S
Integrated Diagnostics
Open-Wire and Short Fault Detection
Undervoltage/Overvoltage Warning
Thermal Shutdown
S
High Flexibility
Interface
SPI
12-Cell and 16-Cell Versions
Minimum (3 Cells) Operation
+6V
+0.5V to +4.5V Cell Voltage Range
Integrated Cell-Balancing FET Drivers
Integrated 5V LDO
S
Low Power
1µA Shutdown Mode
1µA/10µA Cell Current Draw
Ordering Information
appears at end of data sheet.
Functional Diagram
appears at end of data sheet.
For related parts and recommended products to use with this part,
refer to
www.maximintegrated.com/MAX14920.related.
Applications
Industrial Battery Backup Systems
Telecom Battery Backup Systems
Energy Storage Packs
e-Transportation Energy Packs
For pricing, delivery, and ordering information, please contact Maxim Direct
at 1-888-629-4642, or visit Maxim’s website at www.maximintegrated.com.
19-6496; Rev 0; 10/12
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to AGND.)
V
P
to AGND ..........................................................-0.3V to +70V
LDOIN to AGND ............................... (V
A
- 0.3V) to (V
P
+ 0.3V)
V
A
to AGND ............................................................-0.3V to +6V
CV0, DGND to AGND ..........................................-0.3V to +0.3V
SCLK, SDI,
CS,
EN ..................................................-0.3V to +6V
SDO, SAMPL ............................................... -0.3V to (V
L
+ 0.3V)
CV1 to AGND ..........................................................-0.3V to +6V
CV2–CV12 to AGND..............(V
CV
(n* - 1) - 0.3V) to (V
P
+ 0.3V)
CT1–CT12 to AGND .................... -0.3V to (V
CV1
–V
CV12
+ 0.3V)
CB2–CB12 to AGND ....................... -0.3V to (V
CV(n* - 1)
+ 0.3V)
CV2–CV16 to AGND
(MAX14921 only) .............. (V
CV(m** - 1)
- 0.3V) to (V
P
+ 0.3V)
CT1–CT16 to AGND
(MAX14921 only) ......................-0.3V to (V
CV1–
V
CV16
+ 0.3V)
CB2–CB16 to AGND
(MAX14921 only) .......................-0.3V to (V
CV(m** - 1)
+ 0.3V)
BA1 to AGND ......................................... -0.3V to (V
CV1
+ 0.3V)
BA2–BA12 to
AGND ........(V
CV(n* - 1)
- 0.3V) to min((V
CVn*
+ 0.3V) or +6V)
BA2–BA16 to AGND
(MAX14921 only) ...........................(V
CV(m** - 1)
- 0.3V) to min
((V
CVm**
+ 0.3V) or +6V)
AOUT, T1, T2, T3 to AGND ......................... -0.3V to (V
A
+ 0.3V)
Continuous Power Dissipation (T
A
= +70°C)
64-Pin TQFP-EP (derate 31.3mW/°C above +70°C)...2508mW
80-Pin TQFP (derate 23.3mW/°C above +70°C) ........1860mW
Operating Temperature Range .......................... -40NC to +85°C
Maximum Junction Temperature.....................................+150°C
Storage Temperature Range............................ -65NC to +150°C
Lead Temperature (soldering, 10s) ................................+300°C
Soldering Temperature (reflow) ......................................+260°C
*n
= 2–12
**m
= 2–16
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional opera-
tion of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PACKAGE THERMAL CHARACTERISTICS (Note 1)
Junction-to-Ambient Thermal Resistance (q
JA
)
64-Pin TQFP-EP..........................................................31.9°C/W
80-Pin TQFP ..................................................................43°C/W
Junction-to-Case Thermal Resistance (q
JC
)
64-Pin TQFP-EP...............................................................1°C/W
80-Pin TQFP ....................................................................8°C/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
DC ELECTRICAL CHARACTERISTICS
(V
P
= +65V, DGND = AGND, V
L
= V
EN
= +3.3V, V
A
= +5V, C
SAMPLE
= 1FF, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 2)
PARAMETER
POWER SUPPLIES
V
P
Supply Voltage
V
P
Supply Current
LDOIN Supply Voltage
LDOIN Supply Current
V
A
Analog Supply Voltage
V
A
Analog Supply Current
V
L
Supply Voltage
V
L
Supply Current
Maxim Integrated
SYMBOL
V
P
I
P_OFF
I
P_ON
V
LDOIN
I
LDOIN_OFF
I
LDOIN_ON
V
A
I
A_OFF
I
A_ON
V
L
I
L
CONDITIONS
MIN
+6
TYP
MAX
+65
1
UNITS
V
FA
V
FA
V
FA
V
FA
2
EN = low or LOPW = 1
EN = high
+6
EN = low, I
A
= 0A
EN = high, I
A
= 0A
V
A
supply externally, V
A
= V
LDOIN
EN = low, V
A
= V
LDOIN
EN = high, V
A
= V
LDOIN
+1.62
All logic inputs static, held at logic-low
or logic-high
2.5
+4.75
75
350
+5
50
350
65
150
+65
125
500
+5.25
75
450
+5.5
5
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(V
P
= +65V, DGND = AGND, V
L
= V
EN
= +3.3V, V
A
= +5V, C
SAMPLE
= 1FF, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 2)
PARAMETER
V
P
UVLO
UVLO Hysteresis
LDOIN UVLO
V
A
UVLO
V
L
UVLO
LDO Output Voltage
ANALOG INPUTS (T1, T2, T3)
Input Signal Range
On-Resistance
Input Leakage Current
CAPACITOR INPUTS (CT_)
Capacitor Discharge Current
ANALOG INPUTS (CV_)
Differential Input Signal Range
for Guaranteed Accuracy
CV1 Input Voltage Range
CV2–CV12 Input Voltage Range
(MAX14920)
CV2–CV16 Input Voltage Range
(MAX14921)
V
Dn
V
CV1
V
CVn
V
CVm
I
LS_
Input Leakage Current
I
LH_
I
LC_
I
LD_
Balancing Input Current
I
LB_
R
SAMPLE
R
SWCAL
Cell Undervoltage Threshold
Cell Overvoltage Threshold
UV_V
CVTH
OV_V
CVTH
n ≥ 2, V
CVn
≥ V
CVn-1
(Note 3)
m ≥ 2, V
CVm
≥ V
CVm-1
(Note 3)
During sampling phase
During holding phase
During calibration
During diagnostics, DIAG = 1
BA_ active, V
CVn
- V
CVn-1
= +4.5V
(Note 3)
V
CVn
> +2V, I
SINK
= 2mA (Note 3)
V
CVn
> +1.5V, I
SINK
= 1mA (Note 3)
V
CVn
> +2V, I
SINK
= 2mA (Note 3)
An undervoltage sets the associated SPI
Cn bit
An overvoltage sets the associated SPI
Cn bit
+1.4
V
CVn
– V
CVn-1
(Note 3)
+0.5
0
+1.5
+1.5
-1
-1
-1
10
6.5
80
90
800
+1.5
V
A
16,000
+1.6
V
V
12
150
I
mA
+4.5
+5
+65
+65
+1
+10
+10
FA
V
V
V
V
I
LT_
Hold phase, SAMPL = low
-1
+1
FA
V
T
R
ONA
I
T_LEAK
T_ route to buffer amplifier
T_ route to AOUT
-1
-1
Reference to AGND
0
V
A
200
+1
+1
V
I
FA
SYMBOL
UV_V
PVTH
UV_V
PHYST
UV_LDOIN
VT
UV_V
AVTH
UV_V
LVTH
V
A_LDO_OUT
V
LDOIN
rising
V
A
rising
V
L
rising
0 < I
LOAD
< 10mA
+4.75
+5
+5.25
V
P
rising
200
+6
+4.7
+1.6
+5.25
CONDITIONS
MIN
TYP
MAX
+6
UNITS
V
mV
V
V
V
V
Sample Switch On-Resistance
Maxim Integrated
3
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(V
P
= +65V, DGND = AGND, V
L
= V
EN
= +3.3V, V
A
= +5V, C
SAMPLE
= 1FF, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 2)
PARAMETER
ANALOG OUTPUT (AOUT)
Output Signal Range
Amplifier Offset Voltage
Temperature Offset Drift
Gain
Output Error
Amplifier Gain Error
V
P
Monitor Voltage
V
P
Monitor Accuracy
A_V
V
O_ERR
V
GAIN_ERR
V
PMON
V
PMONA
V
AOUT
V
OFFSET
Reference to AGND
V
AOUT
= +3.3V, after self-calibration
(Note 5)
If not recalibrated
Gain = V
AOUT/
V
D
(Note 4)
R
OUT
= 100kI, V
D
= 2V to 4.5V (Note 6)
[SC0, SC1, SC2, SC3]
= [0, 0, 1, 1]
[SC0, SC1, SC2, SC3] =
[0, 0, 1, 1]
I
BA_
= 1mA, V
CV(n)
- V
CV(n - 1)
= +3.3V
(Note 3)
I
BA_
= -1mA, V
CV(n)
- V
CV(n - 1)
= +3.3V
(Note 3)
MAX14920
MAX14921
-0.25
-0.5
-0.2
V
P
/12
V
P
/16
0
+2.5
+0.3
Q50
Q1.5
1
+0.5
+0.2
V
A
- 0.3
Q100
V
FV
FV/°C
V/V
mV
mV
V
%
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
CHARGE-BALANCE DRIVERS (BA_)
Output Low
Output High
Pulldown Resistance
LOGIC OUTPUT (SDO)
Output Low Voltage
Output High Voltage
Output Leakage Current
V
OL
V
OH
I
L
I
SINK
= 10mA
I
SOURCE
= 0.5mA
V
CS
= V
L
V
L
< +2.3V
+2.3V < V
L
< +5.5V
V
L
< +2.3V
+2.3V < V
L
< +5.5V
0.8 x V
L
0.7 x V
L
-1
Measured between channels with
+4V signal change. Settling to
Q1mV
accuracy, C
LOAD
= 100pF (Figure 1)
C
SAMPLE
= 1FF
C
SAMPLE
= 1FF, error calibration
Delay from
SMPLB
set to 1 or SAMPL
falling edge to holding of all cell voltages
4
40
0.5
+1
V
L
- 0.25
-1
+1
0.2 x V
L
0.3 x V
L
+0.9
V
V
FA
V
BAL
V
BAH
R
PDWN
V
CV(n - 1)
V
CV(n)
- 1.5
0.65
V
CV(n - 1)
+ 0.9
V
CV(n)
0.9
V
V
kI
LOGIC INPUTS (SDI, SCLK, EN, SAMPL)
Input Low Voltage
Input High Voltage
Input Leakage Current
DYNAMIC CHARACTERISTICS
AOUT Settling Time
t
SET
5
Fs
V
IL
V
HL
I
L
V
V
FA
Sampling Time
Holding Delay Time
Maxim Integrated
t
SAMPL
t
HD
ms
Fs
4
MAX14920/MAX14921
High-Accuracy 12-/16-Cell Measurement AFEs
DC ELECTRICAL CHARACTERISTICS (continued)
(V
P
= +65V, DGND = AGND, V
L
= V
EN
= +3.3V, V
A
= +5V, C
SAMPLE
= 1FF, T
A
= -40°C to +85°C, unless otherwise noted. Typical
values are at T
A
= +25°C.) (Note 2)
PARAMETER
Level-Shifting Delay Time
AOUT Voltage-Droop Time
T_ Settling Time
T_ Turn-On Delay Time
SYMBOL
t
LS_DELAY
t
DROOP
t
TS
t
TD
t
VPS
Measured between V
P
/12 (MAX14920),
V
P
/16 (MAX14921) input selection and
AOUT, settling to 2.5%,
C
LOAD
= 100pF, SC3 = 1
25
CONDITIONS
Delay from
SMPLB
set to 1 or SAMPL
falling edge to shifting of all cell voltages
to ground and available for reading
Droop to -1mV (Figure 2)
Measured between T_ input selection
and AOUT settling to +1mV accuracy,
C
LOAD
= 100pF, SC2 = 1
1
5
0.2
MIN
TYP
25
MAX
50
UNITS
Fs
ms
Fs
Fs
V
P
Settling Time
Self-Calibration Time
THERMAL DETECTION
Thermal Shutdown
Thermal-Shutdown Hysteresis
SPI TIMINGS (Figure 3)
SDI to SCLK Setup
SDI to SCLK Hold
SCLK to SDO Valid
CS
Fall to SDO Enable
CS
Rise to SDO Disable
CS
Pulse Width
CS
Fall to SCLK Rise Setup
CS
Rise to SCLK Rise Hold
SCLK High Pulse Width
SCLK Low Pulse Width
SCLK Period
60
Fs
8
+140
15
t
DS
t
DH
t
DO
t
DV
t
TR
t
CSW
t
CSS
t
CSH
t
CH
t
CL
t
CP
65
65
208
50
100
0
50
12
100
100
80
ms
°C
°C
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 2:
All devices are 100% production tested at T
A
= +25°C. Limits over the operating temperature range are guaranteed by design.
Note 3:
Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921).
Note 4:
Output error V
O_ERR
is the difference between the input cell difference voltage (V
D
= V
CV(n)
- V
CV(n - 1)
) and the
output voltage V
AOUT
. Where n = 1–12 (MAX14920) and n = 1–16 (MAX14921). Output error depends on buffer ampli-
fier errors and parasitic capacitance charge injection error. Since parasitic capacitance error is PCB dependent, output
error is guaranteed by design for a sampling capacitor of 1FF and parasitic capacitance less than 2.5pF on CTn (see the
Measurement Accuracy
section for a detailed explanation).
Note 5:
Buffer amplifier self-calibrates its offset at power-up and every time it is requested. Due to possible thermal drift after
power-up phase, it is suggested to run self-calibration on a regular basis to get best performance
(see the
Buffer Amplifier Offset Calibration
section for a detailed explanation).
Note 6:
Amplifier error is the sum of all errors including amplifier offset and gain error.
Maxim Integrated
5
stm32/stm8
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