GenClock
™
MK1573-02
HSYNC to Video Clock
Description
The MK1573 GenClock™ provides genlock
timing for video overlay systems. The device
accepts the horizontal sync (HSYNC) signal as the
input reference clock, and generates a frequency-
locked high speed output. Stored in the device are
the multipliers for 16 combinations of popular
frequencies for analog and digital TV and set-top
box systems. Frequency-locked outputs include
1X, 4X, and 8X the subcarrier frequencies of
NTSC and PAL systems, and 27MHz plus
13.5MHz for digital video systems. In most
selections, the chip recovers the HSYNC clock by
outputting a low jitter 50% duty cycle version of
HSYNC. Also available is an inverted recovered
HSYNC clock, and a double speed recovered
HSYNC clock.
MicroClock can customize this device for any
other different frequencies.
Features
• Packaged in 16 pin narrow (150 mil) SOIC
• The -02 version has one frequency changed
(32MHz was added), and tracks the HSYNC
better than the -01 version.
• Exact ratios stored in the device eliminate the need
for external dividers
• Accepts HSYNC of 15.625kHz or 15.73426kHz
• Highly accurate frequency generation within 1 ppm
• Generates NTSC/PAL subcarrier frequencies, and
4X and 8X of those frequencies
• Generates 27MHz and 13.5MHz
• 2X HSYNC clock available
• Recovered HSYNC clock available
• Inverted HSYNC clock available
• 4.5V to 5.5V operation
Block Diagram
VDD
GND
2
FS0-3
4
2
Clock
Synthesis
and
Control
Circuitry
Output
Buffer
Output
Buffer
Output
Buffer
CLK1
CLK2
CLK3
HSYNC
Input Clock
Input
Buffer
OE (all outputs)
MDS 1573-02 B
1
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
GenClock
™
Pin Assignment
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
FS3
N/C
FS2
FS1
CLK2
OE
CLK1
CLK3
MK1573-02
HSYNC to Video Clock
Output Clocks Decoding Table MK1573-02 (MHz)
Decode Address
FS3:0 (Hex)
0
0000
1
0001
2
0010
3
0011
4
0100
5
0101
6
0110
7
0111
8
1000
9
1001
A
1010
B
1011
C
1100
D
1101
E
1110
F
1111
HSYNC Multiplier
CLK 1
CLK 2
CLK 3
pin 1
On-chip
pin 10
pin 12
pin 9
15.625k
1536
24M
12M
15.625k
15.734264k 1525 1/3
24M
12M
15.734264k
15.625k
1728
27M
13.5M
15.625k
15.734264k
1716
27M
13.5M
15.734264k
15.625k
960
15M
7.5M
15.625k
15.734264k 953 1/3
15M
7.5M
15.734264k
15.625k
3840
60M
30M
15.625k
15.734264k
3840
60.41957M 30.20979M
15.734264k
15.625k
2270
35.46875M 17.734375M 4.433594M
15.734264k
1820
28.63636M 14.31818M 3.579545M
15.625k
2270
35.46875M
15.625k
15.625k
15.734264k
1820
28.63636M
15.734264k 15.734264k
15.625k
2048
32M
16M
15.625k
15.734264k
808
12.71329M
15.734264k
31.4685k
15.625k
2270
35.46875M
15.625k
31.25k
15.734264k
1820
28.63636M
15.734264k
31.4685k
16 pin (150 mil) SOIC
• 0 = connect directly to ground, 1 = connect directly to VDD.
• CLK2 is a recovered HSYNC (with 50% duty cycle) on selections in italic.
• HSYNC reference outputs on CLK3 (in italic) are inverted, recovered HSYNC.
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Name
HSYNC
VDD
VDD
CAP1
GND
CAP2
GND
FS0
CLK3
CLK1
OE
CLK2
FS1
FS2
N/C
FS3
Type
I
P
P
I
P
I
P
I
O
O
I
O
I
I
-
I
Description
HSYNC clock input. The output clocks are synchronized to the HSYNC falling edge.
Connect to +5V.
Connect to +5V.
Connect a 0.01µF ceramic capacitor and a 39kΩ resistor in series between this pin and CAP2.
Connect to ground.
Connect a 0.01µF ceramic capacitor and a 39kΩ resistor in series between this pin and CAP1.
Connect to ground.
Frequency Select 0. Determines CLK outputs (with given input) per table above.
Clock 3 determined by status of FS3:0 per table above.
Clock 1 determined by status of FS3:0 per table above.
Output Enable. Tri-states the three output clocks when low.
Clock 2 determined by status of FS3:0 per table above.
Frequency Select 1. Determines CLK outputs (with given input) per table above.
Frequency Select 2. Determines CLK outputs (with given input) per table above.
No Connect. Nothing is connected to this pin.
Frequency Select 3. Determines CLK outputs (with given input) per table above.
Type: I = Input, O = output, P = power supply connection
MDS 1573-02 B
2
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
GenClock
™
External Components/Crystal Selection
MK1573-02
HSYNC to Video Clock
The MK1573 requires a minimum number of external components for proper operation. A 0.1µF low
leakage capacitor (see Capacitor Selection on following page) should be connected between CAP1 and
CAP2 as close to the chip as possible. A high quality ceramic capacitor is recommended. A decoupling
capacitor of 0.1µF must be connected between VDD and GND pins (pins 2 and 3, 5 and 7) close to the
chip, and 33Ω terminating resistors can be used on clock outputs with traces longer than 1 inch.
Electrical Specifications
Parameter
Supply Voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage Temperature
Operating Voltage, VDD
Input High Voltage, VIH
Input Low Voltage, VIL
Output High Voltage
Output High Voltage
Output Low Voltage
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Actual mean frequency error versus target, note 2
Input Frequency, NTSC
Input Frequency, PAL
Output Clock Rise Time
Output Clock Fall Time
Output Clock Duty Cycle, High Time
Absolute Clock Period Jitter
Output Enable Time, OE high to outputs on
Output Disable Time, OE low to tri-state
Conditions
Referenced to GND
-0.5
0
Max of 10 seconds
-65
4.5
2
IOH=-4mA
IOH=-25mA
IOL=25mA
No Load, VDD=5.0V
Each output
Any clock selection
VDD-0.4
2.4
0.4
15
±100
7
0
15.734264
15.625
0.8 to 2.0V
2.0 to 0.8V
At VDD/2
1.5
1.5
60
50
3
Minimum
Typical
Maximum
7
VDD+0.5
70
250
150
5.5
0.8
Units
V
V
°C
°C
°C
V
V
V
V
V
V
mA
mA
pF
ppm
kHz
kHz
ns
ns
%
ps
ns
µs
ABSOLUTE MAXIMUM RATINGS (Note 1)
DC CHARACTERISTICS (VDD = 5V unless noted)
1
AC CHARACTERISTICS (VDD = 5V unless noted)
40
49 to 51
TBD
Notes:
1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged exposure
to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. Most selections have zero ppm error. Some selections have a maximum of 1 ppm synthesis error .
MDS 1573-02 B
3
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
GenClock
™
Loop Bandwidth and Loop Filter Component Selection
MK1573-02
HSYNC to Video Clock
The series connected capacitor and resistor between CAP1 and CAP2 (pins 4 and 6) determine the dynamic
characteristics of the phase-locked loop. The capacitor must have very low leakage, therefor a high quality
ceramic capacitor is recommended. DO NOT use any type of polarized or electrolytic capacitor. The values
of the RC network determine the bandwidth of the PLL.
The tracking of the jitter on the HSYNC input improves with increasing values of R and decreasing values of
C, until a point is reached where the loop starts becoming unstable. At that point, HSYNC tracking becomes
unreliable. Loop filter values between 470pF and 0.01µF, and 18kΩ and 120kΩ will work for most
application where the PLL must track HSYNC jitter with minimum error. A good starting point is 680pF
and 82kΩ. The optimum values should be determined by the spectral characteristics of the HSYNC jitter.
The following formula gives the approximate loop bandwidth for the MK1573:
f
bw
537
=
where:
f
clk1 • C
537
f
bw is the loop bandwidth in Hertz
f
clk1 is the frequency of CLK1 in Hertz
C
is the value of capacitor in Farads
For example, if CLK1 is running at 24MHz and C=1000pF, then
f
bw
=
24x10
6
• 1x10
-9
= 3.47kHz
If minimum absolute jitter is required, the RC network should be replaced by a single capacitor with a value
between 0.01µF and 2µF. Larger values will cause the PLL to start more slowly. For example, if C=2µF, the
loop may take several seconds to start.
PC Board Layout
A proper board layout is critical to the successful
use of the MK1573. In particular, the CAP1 and
CAP2 pins are very sensitive to noise and leakage
(CAP1 at pin 4 is the most sensitive). Traces
must be as short as possible and the capacitor
and resistor must be mounted next to the device
as shown to the right. The capacitor connected
between pins 3 and 5 is the power supply
decoupling capacitor.
The high frequency output clocks on CLK1 and
CLK2 may benefit from a series 33Ω resistor
connected close to the pin (not shown).
V
cap
cap
G
resist.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
V
=connect to VDD
G
=connect to GND
Video Clock Multipliers/Accuracies
In the table on page 2 are the actual multipliers stored in the MK1573-02 ROM, which shows that the
accuracies are within one ppm for the output clocks.
MDS 1573-02 B
4
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
GenClock
™
Clock Waveforms
MK1573-02
HSYNC to Video Clock
In addition to generating the video clock on CLK1 (pin 10), the MK1573 also outputs the recovered
HSYNC clocks. On certain selections, a double speed recovered HSYNC clock is also available. These
recovered clocks will have lower jitter than the HSYNC input due to the filtering action of the PLL. The
jitter spectrum of the recovered clocks will be reduced at frequencies higher than the loop bandwidth. The
above section describes how to calculate the approximate loop bandwidth. The waveforms of the
recovered clocks fall into one of three different groups depending on the address selection:
Addresses 0 to 7 and C
HSYNC
input
CLK3
Addresses A and B
HSYNC
input
CLK2
CLK3
Addresses D, E, and F
HSYNC
input
CLK2
CLK3
The recovered clocks are triggered by the falling edge of HSYNC and are delayed by about 100ns.
MDS 1573-02 B
5
Revision 120497
Printed 11/15/00
Integrated Circuit Systems, Inc. • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•www.icst.com
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