MK2058-01
Communications Clock Jitter Attenuator
Description
The MK2058-01 is a VCXO (Voltage Controlled Crystal
Oscillator) based clock jitter attenuator designed for
system clock distribution applications. This monolithic
IC, combined with an external inexpensive quartz
crystal, can be used to replace a more costly hybrid
VCXO retiming module. The device accepts and
outputs the same clock frequency in selectable ranges
covering 4kHz to 27MHz. A dual input mux is also
provided.
By controlling the VCXO frequency within a
phase-locked loop (PLL), the output clock is phase and
frequency locked to the input clock. Through selection
of external loop filter components, the PLL loop
bandwidth and damping factor can be tailored to meet
system clock requirements. A loop bandwidth down to
the Hz range is possible.
Features
•
Excellent jitter attenuation for telecom clocks
•
Also serves as a general purpose clock jitter
•
•
•
•
•
•
•
•
•
attenuator for distributed system clocks and
recovered data or video clocks
2:1 Input MUX for input reference clocks
VCXO-based clock generation offers very low jitter
and phase noise generation
Output clock is phase and frequency locked to the
selected input reference clock
Fixed input to output phase relationship
+115ppm minimum crystal frequency pullability
range, using recommended crystal
Industrial temperature range
Low power CMOS technology
20 pin SOIC package
Single 3.3V power supply
Block Diagram
P u llable xtal
VD D
ISE T
X1
X2
VDD
3
In p ut C lock
In p ut C lock
IC LK 2
IC LK 1
1
0
Ph ase
D etecto r
C h arge
P um p
VC X O
Selectable
D ivider
C LK
IS EL
S EL 2:0
3
CHGP
V IN
GND
4
MDS 2058-01 B
1
Revision 071001
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK2058-01
Communications Clock Jitter Attenuator
Pin Assignment
X1
VD D
VD D
VD D
V IN
GN D
GN D
GN D
CHG P
ISE T
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
GND
IS E L
IC L K 1
IC L K 2
S EL 0
CLK
NC
S EL 1
S EL 2
Output Clock Selection Table
SEL2 SEL1 SEL0
0
0
0
0
M
M
M
M
1
1
1
1
0
0
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
0
1
Input / Output
Range
4.4 to 8.79 kHz
1 to 1.6 MHz
1.6 to 2.7 MHz
2.7 to 4.5 MHz
6.6 to 13.2 kHz
7.8 to 15.734kHz
64 to 70 kHz
105 to 210 kHz
4.0 to 6.8 MHz
5.5 to 9 MHz
8.5 to 13.5 MHz
13.5 to 27 MHz
Crystal
Frequency
3072 x ICLK
16 x ICLK
10 x ICLK
6 x ICLK
2048 x ICLK
1716 x ICLK
384 x ICLK
128 x ICLK
4 x ICLK
3 x ICLK
2 x ICLK
1 x ICLK
20 pin 300 mil SOIC
Note: For SEL input pin programming:
0 = GND, 1 = VDD, M = Floating
Pin Descriptions
Pin
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Pin
Name
X1
VDD
VDD
VDD
VIN
GND
GND
GND
CHGP
ISET
SEL2
SEL1
NC
CLK
SEL0
ICLK2
ICLK1
ISEL
GND
X2
Pin
Type
-
Power
Power
Power
Input
Power
Power
Power
Output
-
Input
Input
Input
Output
Input
Input
Input
Input
Power
-
Pin Description
Crystal Input. Connect this pin to the specified crystal.
Power Supply. Connect to +3.3V.
Power Supply. Connect to +3.3V.
Power Supply. Connect to +3.3V.
VCXO Control Voltage Input. Connect this pin to CHGP pin and the external
loop filter as shown in this data sheet.
Connect to ground
Connect to ground
Connect to ground
Charge Pump Output. Connect this pin to the external loop filter and to pin
VIN.
Charge pump current setting node, connection for setting resistor.
Output Frequency Selection Pin 2. Determines output frequency as per table
above. Internally biased to VDD/2.
Output Frequency Selection Pin 1. Determines output frequency as per table
above. Internal pull-up.
No Internal Connection.
Clock Output
Output Frequency Selection Pin 0. Determines output frequency as per table
above. Internal pull-up.
Input Clock Connection 2. Connect an input reference clock to this pin. If
unused, connect to ground.
Input Clock Connection 1. Connect an input reference clock to this pin. If
unused, connect to ground.
Input Selection. Used to select which reference input clock is active. Low input
level selects ICLK1, high input level selects ICLK2. Internal pull-up.
Connect to ground.
Crystal Output. Connect this pin to the specified crystal.
MDS 2058-01 B
2
Revision 071001
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK2058-01
Communications Clock Jitter Attenuator
Functional Description
The MK2058-01 is a clock generator IC that generates
an output clock directly from an internal VCXO circuit
which works in conjunction with an external quartz
crystal. The VCXO is controlled by an internal PLL
(Phase Locked Loop) circuit, enabling the device to
perform clock regeneration from an input reference
clock. The MK2058-01 is configured to provide an
output clock that is the same frequency as the input
clock. There are 12 selectable input / output frequency
ranges, each of which is a submultiple of the supported
quartz crystal frequency range. Please refer to the
Output Clock Selection Table on Page 2.
Most typical PLL clock devices use an internal VCO
(Voltage Controlled Oscillator) for output clock
generation. By using a VCXO with an external crystal,
the MK2058-01 is able to generate a low jitter, low
phase-noise output clock within a low bandwidth PLL.
This serves to provide input clock jitter attenuation and
enables stable operation with a low frequency
reference clock.
The VCXO circuit requires an external pullable crystal
for operation. External loop filter components enable a
PLL configuration with low loop bandwidth.
output clock will change to reflect the phase of the
newly selected input at a controlled phase slope (rate
of phase change) as influenced by the PLL loop
characteristics.
Quartz Crystal
It is important that the correct type of quartz crystal is
used with the MK2058-01. Failure to do so may result
in reduced frequency pullability range, inability of the
loop to lock, or excessive output phase jitter.
The MK2058-01 operates by phase-locking the VCXO
circuit to the input signal of the selected ICLK input.
The VCXO consists of the external crystal and the
integrated VCXO oscillator circuit. To achieve the best
performance and reliability, a crystal device with the
recommended parameters (shown below) must be
used, and the layout guidelines discussed in the PCB
Layout Recommendations section must be followed.
The frequency of oscillation of a quartz crystal is
determined by its cut and by the external load
capacitance. The MK2058-01 incorporates variable
load capacitors on-chip which “pull”, or change, the
frequency of the crystal. The crystals specified for use
with the MK2058-01 are designed to have zero
frequency error when the total of on-chip + stray
capacitance is 14pF. To achieve this, the layout should
use short traces between the MK2058-01 and the
crystal.
A complete description of the recommended crystal
parameters is shown below.
Recommended Crystal Parameters:
Operating Temperature Range
Commercial Applications
Industrial Applications
Initial Accuracy at 25
°
C
Temperature Stability
Aging
Load Capacitance
Shunt Capacitance, C0
C0/C1 Ratio
Equivalent Series Resistance
0 to 70
°
C
-40 to 85
°
C
±20 ppm
±30 ppm
±20 ppm
Note 1
7 pF Max
250 Max
35
Ω
Max
Application Information
Input / Output Frequency Configuration
The MK2058-01 is configured to generate an output
frequency that is equal to the input reference
frequency. Clock frequencies that are supported are
those which fall into the ranges listed in the Output
Clock Selection Table on Page 2. Input bits SEL2:0 are
set according to this table, as is the external crystal
frequency. The nominal (center) frequency of the
external crystal will be an integer multiple of the input /
output clock as specified. Please refer to the Quartz
Crystal section on this page regarding external crystal
requirements.
Input Mux
The Input Mux serves to select between two alternate
input reference clocks. Upon reselection of the input
clock, clock glitches on the output clock will not be
generated due to the “fly-wheel” effect of the VCXO
(the quartz crystal is a high-Q tuned circuit). When the
input clocks are not phase aligned, the phase of the
Note 1: For crystal frequencies between 13.5MHz and
27MHz the nominal crystal load capacitance
specification should be 14pF. Contact ICS MicroClock
applications at (408) 297-1201 regarding the use of a
crystal below 13.5MHz.
MDS 2058-01 B
3
Revision 071001
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK2058-01
Communications Clock Jitter Attenuator
To obtain a list of qualified crystal devices that meet
these requirements, please contact ICS MicroClock
applications department.
External Component Schematic
C
L
Do n’t S tuff
(R efer to O ptio nal
C ry stal T uning
section)
X1
VDD
VDD
VDD
VIN
C
L
PLL Loop Filter Components
All analog PLL circuits use a loop filter to establish
operating stability. The MK2058-01 uses external loop
filter components for the following reasons:
1) Larger loop filter capacitor values can be used,
allowing a lower loop bandwidth. This enables the use
of lower input clock reference frequencies and also
input clock jitter attenuation capabilities. Larger loop
filter capacitors also allow higher loop damping factors
when less passband peaking is desired.
2) The loop filter values can be user selected to
optimize loop response characteristics for a given
application.
Referencing the External Component Schematic on
this page, the external loop filter is made up of the
components R
Z
, C
1
and C
2
. R
SET
establishes PLL
charge pump current and therefore influences loop
filter characteristics.
Xtal
1
2
3
4
5
6
7
8
9
10
20
19
18
17
16
15
14
13
12
11
X2
G ND
IS EL
IC LK 1
IC LK 2
S EL0
C LK
NC
S EL1
S EL2
C
2
R
Z
C
1
G ND
G ND
G ND
C HG P
IS ET
R
S ET
Recommended Loop Filter Values Vs. Output Frequency Range Selection
Crystal
SEL2 SEL1 SEL0
Multiplier
(N)
0
0
0
3072
0
0
1
16
0
1
0
10
0
1
1
6
M
0
0
2048
M
0
1
1716
M
1
0
384
M
1
1
128
1
0
0
4
1
0
1
3
1
1
0
2
1
1
1
1
R
SET
R
Z
C
1
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
0.1
µF
C
2
Loop
Bandwidth
(-3dB point)
Damping
Factor
1
1
1
1
1
1
1
1
1
1
1
1
120 kΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
540 kΩ
540 kΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
1.4 MΩ
750 kΩ
160 kΩ
130 kΩ
100 kΩ
1.2 MΩ
1.1 MΩ
820 kΩ
470 kΩ
82 kΩ
68 kΩ
56 kΩ
39 kΩ
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
4.7 nF
14 Hz
60 Hz
75 Hz
95 Hz
8.5 Hz
9 Hz
12 Hz
20 Hz
120 Hz
130 Hz
160 Hz
225 Hz
Note: For SEL input pin programming: 0 = GND, 1 = VDD, M = Floating
MDS 2058-01 B
4
Revision 071001
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
MK2058-01
Communications Clock Jitter Attenuator
A “normalized” PLL loop bandwidth may be calculated
as follows:
R
Z
×
I
CP
×
575
NBW
= ---------------------------------------
-
N
The “normalized” bandwidth equation above does not
take into account the effects of damping factor or the
second pole. However, it does provide a useful
approximation of filter performance.
The loop damping factor is calculated as follows:
625
×
I
CP
×
C
1
Damping Factor = R
Z
×
----------------------------------------
-
N
Where:
R
Z
= Value of resistor in loop filter (Ohms)
I
CP
= Charge pump current (amps)
(refer to Charge Pump Current Table, below)
N = Crystal multiplier shown in the above table
C
1
= Value of capacitor C
1
in loop filter (Farads)
As a general rule, the following relationship should be
maintained between components C
1
and C
2
in the loop
filter:
C
2
1) The loop capacitors should be a low-leakage type to
avoid leakage-induced phase noise. For this reason,
DO NOT use any type of polarized or electrolytic
capacitors.
2) Microphonics (mechanical board vibration) can also
induce output phase noise, especially when the loop
bandwidth is less than 1kHz. For this reason, ceramic
capacitors should have C0G or NP0 dielectric. Avoid
high-K dielectrics like Z5U and X7R. These and some
other ceramics have piezoelectric properties that
convert mechanical vibration into voltage noise that
interferes with VCXO operation.
For larger loop capacitor values such as 0.1
µF
or 1
µF,
PPS film types made by Panasonic, or metal poly types
made by Murata or Cornell Dubilier are recommended.
For questions or changes regarding loop filter
characteristics, please contact your sales area FAE, or
ICS MicroClock Applications.
Series Termination Resistor
Clock output traces over one inch should use series
termination. To series terminate a 50Ω trace (a
commonly used trace impedance), place a 33Ω resistor
in series with the clock line, as close to the clock output
pin as possible. The nominal impedance of the clock
output is 20Ω. (The optional series termination resistor
is not shown in the External Component Schematic.)
-
= -----
20
C
1
Decoupling Capacitors
As with any high performance mixed-signal IC, the
MK2058-01 must be isolated from system power
supply noise to perform optimally.
Decoupling capacitors of 0.01µF must be connected
between each VDD and the PCB ground plane. To
further guard against interfering system supply noise,
the MK2058-01 should use one common connection to
the PCB power plane as shown in the diagram on the
next page. The ferrite bead and bulk capacitor help
reduce lower frequency noise in the supply that can
lead to output clock phase modulation.
Charge Pump Current Table
R
SET
1.4 MΩ
680 kΩ
540 kΩ
120 kΩ
Charge Pump Current
(I
CP
)
10
µA
20
µA
25
µA
100
µA
Special considerations must be made in choosing loop
components C
1
and C
2
:
MDS 2058-01 B
5
Revision 071001
Integrated Circuit Systems, Inc.
q
525 Race Street, San Jose, CA 95126
q
tel (408) 295-9800
q
www.icst.com
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