input voltage to cause the output clocks to vary by
±100 ppm. Using MicroClock’s patented VCXO
and analog Phase-Locked Loop (PLL) techniques,
the device uses an inexpensive 13.5 MHz crystal
input to produce multiple output clocks including
a selectable processor clock, selectable UART and
audio clocks, a fixed 11.0592 MHz, and two low
skew copies of the 27 MHz. All clocks are
frequency locked to the 27.00 MHz output (and
to each other) with zero ppm error, so any output
can be used as the VCXO output.
This chip directly replaces the MK2771-02 when a
13.5 MHz input crystal is substituted for the
14.31818 MHz used on the -02. Additionally, the
-12 adds 24.576 MHz to the ACLK.
MK2771-12
VCXO and Set-Top Clock Source
Features
• Packaged in 20 pin SOIC
• Pin for pin and functional upgrade to MK2771-02
• Uses an inexpensive 13.5 MHz crystal
• On-chip patented VCXO with pull range
of 200 ppm
• VCXO tuning voltage of 0 to 3 V
• Processor frequency of 16.67 MHz, 20 MHz,
32 MHz, 40 MHz, or 50 MHz
• Zero ppm synthesis error in all clocks (all exactly
track 27MHz VCXO) - patented
• 25 mA output drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5 V operating voltage
Block Diagram
2
AVDD VDD
GND
2
3
Output
Buffer
Output
Buffer
Clock
Synthesis
Circuitry
Output
Buffer
Output
Buffer
Processor Clock
11.0592 MHz
3.6864 MHz
or 18.432 MHz
49.152 MHz
or 24.576 MHz
27.000 MHz
13.500 MHz
PCS1:0
UCS
ACS
VIN
13.5 MHz
pullable
crystal
X1
X2
Voltage
Controlled
Crystal
Oscillator
Output 2
Buffers
÷2
Output
Buffer
1
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
MDS 2771-12 A
I C R O
C
LOC K
Pin Assignment
1
2
3
4
5
6
7
8
9
10
MK2771-12
VCXO and Set-Top Clock Source
Processor Clock Select Table
PCS1
0
0
M
M
1
1
PCS0
0
1
0
1
0
1
PCLK (MHz)
50.000
16.667
test
32.000
40.000
20.000
PCS0
X2
X1
AVDD
VIN
VDD
GND
PCLK
UCLK
ACLK
20
19
18
17
16
15
14
13
12
11
ACS
UCS
27M
GND
27M
VDD
GND
11.06M
PCS1
13.5M
0 = connect directly to ground, 1 = connect directly
to VDD, M = leave floating or unconnected
UART Clock Table
UCS
0
1
UCLK (MHz)
18.432
3.6864
ACLK Select Table
ACS
0
1
ACLK (MHz)
49.152
24.576
Pin Descriptions
Number
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Name
PCS0
X2
X1
AVDD
VIN
VDD
GND
PCLK
UCLK
ACLK
13.5M
PCS1
11.06M
GND
VDD
27M
GND
27M
UCS
ACS
Type
I
O
I
P
I
P
P
O
O
O
O
TI
O
P
P
O
P
O
I
I
Description
Processor Clock Select 0. Selects PCLK on pin 8. See table above.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Analog VDD. Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to +5V.
Connect to ground.
Processor clock output determined by status of PCS1,0. See table above.
UART clock output determined by status of UCS. See table above.
49.152 MHz or 24.576 MHz clock output determined by ACS. See table above
13.5 MHz clock output. Divide by two of the 27MHz VCXO output.
Processor Clock Select 1. Selects PCLK on pin 8. See table above.
11.0592 MHz clock output.
Connect to ground.
Connect to +5V.
27.00 MHz VCXO clock output.
Connect to ground.
27.00 MHz VCXO clock output.
UART Clock Select. Selects UCLK on pin 9. See table above.
ACLK Select. Selects ACLK on pin 10. See table above.
Key: I = Input, TI = Tri-level input, O = output, P = power supply connection
2
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
MDS 2771-12 A
I C R O
C
LOC K
Electrical Specifications
Parameter
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Operating Voltage, VDD
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH (except PCS1)
Input Low Voltage, VIL (except PCS1)
Input High Voltage, VIH, PCS1 only
Input Low Voltage, VIL, PCS1 only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
Conditions
MK2771-12
VCXO and Set-Top Clock Source
Minimum
Typical
Maximum
7
VDD+0.5
70
260
150
5.25
2.5
2.5
1.5
0.8
VDD-0.5
0.5
Units
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
mA
mA
pF
ppm
V
ABSOLUTE MAXIMUM RATINGS (note 1)
Referenced to GND
Referenced to GND
Max of 10 seconds
-65
4.75
3.5
2
-0.5
0
DC CHARACTERISTICS (VDD = 5.0V unless noted)
IOH=-25mA
IOL=25mA
IOH=-8mA
No Load, note 2
Each output
All clocks
2.4
0.4
VDD-0.4
60
±100
7
0
0
3
AC CHARACTERISTICS (VDD = 5.0V unless noted)
Input Frequency
13.50000
MHz
Output Clock Rise Time
0.8 to 2.0V
1.5
ns
Output Clock Fall Time
2.0 to 0.8V
1.5
ns
Output Clock Duty Cycle
At 1.4V
40
60
%
Maximum Absolute Jitter, short term
200
ps
Skew of 27 MHz outputs
Rising edges at 1.4V
-500
0
500
ps
27 MHz output pullability, note 3
0V
≤
VIN
≤
3V
±100
ppm
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With PCLK at 50 MHz.
3. With a pullable crystal that conforms to ICS’ specifications.
External Components
The MK2771-12 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between each VDD and GND, and betweeen AVDD and GND,
as close to the MK2771-12 as possible. A series termination resistor of 33
Ω
may be used for each clock
output.The 13.5 MHz crystal must be connected as close to the chip as possible. The 13.5 MHz crystal
should be a parallel mode, pullable, with load capacitance of 16 pF. Consult MicroClock for recommended
suppliers. Only the crystal should be connected to X1 and X2; do not connect load capacitors to these pins.
3
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
MDS 2771-12 A
I C R O
C
LOC K
Package Outline and Package Dimensions
MK2771-12
VCXO and Set-Top Clock Source
20 pin SOIC
Symbol
A
b
c
D
E
H
e
h
L
Q
Inches
Min
Max
0.092 0.104
0.014 0.019
0.009 0.012
0.490 0.512
0.290 0.300
0.394 0.419
.050 BSC
0.016
0.016 0.035
0.003 0.011
Millimeters
Min
Max
2.3368 2.6416
0.356
0.483
0.229
0.305
12.446 13.005
7.366
7.620
10.008 10.643
1.27 BSC
0.406
0.406
0.889
0.076
0.279
E
H
D
Q
e
b
c
h x 45°
A
L
Ordering Information
Part/Order Number
MK2771-12S
MK2771-12STR
Marking
MK2771-12S
MK2771-12S
Shipping packaging
tubes
tape and reel
Package
20 pin SOIC
20 pin SOIC
Temperature
0-70°C
0-70°C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems, Inc. (ICS) assumes no responsibility for either its use or for
the infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use
in normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental
requirements are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize
or warrant any ICS product for use in life support devices or critical medical instruments.
4
Revision 061699
Printed 11/16/00
MicroClock Division of ICS • 525 Race Street • San Jose • CA • 95126•(408)295-9800tel•(408)295-9818fax
模拟与混合信号
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