input voltage to cause the output clocks to vary by
±100 ppm. Using ICS/MicroClock’s patented
VCXO and analog Phase-Locked Loop (PLL)
techniques, the device uses an inexpensive
13.5 MHz pullable crystal input to produce
multiple output clocks including two selectable
processor clocks, a selectable audio clock, two
communications clocks, and three fixed clocks. All
clocks are frequency locked to the 27.00MHz
output (and to each other) with zero ppm error, so
any output can be used as the VCXO output.
Features
• Packaged in 28 pin SSOP (QSOP)
• Ideal for systems using Oak’s MPEG decoders
• On-chip patented VCXO with pull range
of 200ppm
• VCXO tuning voltage of 0 to 3 V
• Processor frequencies include 33.3, 40, 50, 66.6,
81, and 100 MHz
• Audio clocks of 8.192 MHz, 11.2896 MHz,
12.288 MHz and 18.432 MHz
• Zero ppm synthesis error in all clocks (all exactly
track 27 MHz VCXO)
• Uses an inexpensive 13.5 MHz pullable crystal
• Full CMOS output swings with 25 mA output
drive capability at TTL levels
• Advanced, low power, sub-micron CMOS process
• 5 V operating voltage with 3.3 V capable I/O
Block Diagram
3
VDD
GND
VDDIO
2
PCS2:0
ACS1:0
SC
VIN
Output
Buffers
Output
Buffer
Clock
Synthesis
Circuitry
Output
Buffers
Output
Buffer
Processor Clocks
Audio Clock
2
2
Comm. Clocks
54.00 MHz
27.000 MHz
13.500 MHz
13.5 MHz
pullable
crystal
X1
X2
Voltage
Controlled
Crystal
Oscillator
÷2
÷2
Output
Buffer
Output
Buffer
1
Revision 122899
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
MDS 2771-15 E
MK2771-15
VCXO and Set-Top Clock Source
Pin Assignment
PCS0
X2
X1
VDD
VDD
VIN
VDDIO
VDD
SC
GND
PCLK1
PCLK2
PCS1
ACLK
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
ACS1
ACS0
54M
27M
GND
CCLK1
VDD
VDD
PCS2
GND
GND
CCLK2
13.5M
DC
Processor Clock Select Table (MHz)
PCS2
0
0
0
0
1
1
1
1
PCS1
0
0
1
1
0
0
1
1
PCS0
0
1
0
1
0
1
0
1
PCLK1
27.500
33.333
33.326
50.000
32.400
40.000
TEST
TEST
PCLK2
Off
66.666
83.314
100.000
81.000
33.333
TEST
TEST
Audio Clock Table
ACS1 ACS0 ACLK (MHz)
0
0
8.192
0
1
11.2896
1
0
12.288
1
1
18.432
Comm Clock Table (MHz)
SC
0
M
1
CCLK1
18.432
11.0592
11.0592
CCLK2
24.576
18.432
24.576
Pin Descriptions
Number
1
2
3
4, 5, 8
6
7
9
10, 18, 19, 24
11
12
13
14
15
16
17
20
21, 22
23
25
26
27
28
Name
PCS0
X2
X1
VDD
VIN
VDDIO
SC
GND
PCLK1
PCLK2
PCS1
ACLK
DC
13.5M
CCLK2
PCS2
VDD
CCLK1
27M
54M
ACS0
ACS1
Type
I
XO
XI
P
I
P
TI
P
O
O
I
O
-
O
O
I
P
O
O
O
I
I
0 = connect directly to ground, 1 = connect directly
to VDDIO, M = leave floating or unconnected
Description
Processor Clock Select 0. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Crystal connection. Connect to a pullable 13.5 MHz crystal.
Connect to +5V.
Voltage Input to VCXO. Zero to 3V signal which controls the frequency of the VCXO.
Connect to +3.3V or +5V. Amplitude of inputs must, and outputs will, match this.
Communications clock select pin. Biased to M level if floating.
Connect to ground.
Processor Clock output number 1. Determined by status of PCS2:0
Processor Clock output number 2. Determined by status of PCS2:0
Processor Clock Select 1. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Audio Clock Output. Determined by status of ACS1, ACS0 per table above.
Don't Connect anything to this pin.
13.50 MHz VCXO clock output.
Communications Clock Output 2 determined by status of SC per table above.
Processor Clock Select 2. Selects PCLKs on pins 11 and 12. See table above. Int. pull-up.
Connect to +5V.
Communications Clock Output 1 determined by status of SC per table above.
27.00 MHz VCXO clock output.
54.00 MHz VCXO clock output.
Audio Clock Select 0. Selects ACLK on pin 14. See table above. Internal pull-up.
Audio Clock Select 1. Selects ACLK on pin 14. See table above. Internal pull-up.
Key: I = Input; TI = Tri-level input; O = output; P = power supply connection; XI, XO = crystal connections
2
Revision 122899
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
MDS 2771-15 E
MK2771-15
VCXO and Set-Top Clock Source
Electrical Specifications
Parameter
Supply voltage, VDD
Inputs and Clock Outputs
Ambient Operating Temperature
Soldering Temperature
Storage temperature
Operating Voltage, VDD
Operating Voltage, VDDIO
Input High Voltage, VIH, X1 pin only
Input Low Voltage, VIL, X1 pin only
Input High Voltage, VIH (except SC & PCS2)
Input Low Voltage, VIL (except SC & PCS2)
Input High Voltage, VIH, SC & PCS2 only
Input Low Voltage, VIL, SC & PCS2 only
Output High Voltage, VOH
Output Low Voltage, VOL
Output High Voltage, VOH, CMOS level
Operating Supply Current, IDD+IDDIO (3.3V)
Short Circuit Current
Input Capacitance
Frequency synthesis error
VIN, VCXO control voltage
Conditions
Referenced to GND
Referenced to GND
Max of 10 seconds
-65
4.75
3.15
3.5
2
0.8
VDDIO-0.5
0.5
IOH=-25mA
IOL=25mA
IOH=-8mA
No Load, note 2
Each output
Except X1, X2
All clocks
2.4
0.4
VDDIO-0.4
46+27
±100
7
0
0
3
Minimum
Typical
Maximum
7
VDDIO+0.5
70
260
150
5.25
5.25
2.5
2.5
1.5
Units
V
V
°C
°C
°C
V
V
V
V
V
V
V
V
V
V
V
mA
mA
pF
ppm
V
ABSOLUTE MAXIMUM RATINGS (note 1)
-0.5
0
DC CHARACTERISTICS (VDD, VDDIO = 5.0V unless noted)
for all inputs/outputs
AC CHARACTERISTICS (VDD, VDDIO = 5.0V unless noted)
Input Frequency
13.500000
MHz
Output Clock Rise Time
0.8 to 2.0V, no load
1.5
ns
Output Clock Fall Time
2.0 to 0.8V, no load
1.5
ns
Output Clock Duty Cycle
At VDDIO/2
40
50
60
%
Maximum Absolute Jitter, short term
300
ps
VCXO Pullability
Note 3
-100
100
ppm
Notes: 1. Stresses beyond those listed under Absolute Maximum Ratings could cause permanent damage to the device. Prolonged
exposure to levels above the operating limits but below the Absolute Maximums may affect device reliability.
2. With PCLK at 100 MHz.
3. With a pullable crystal that conforms to ICS’ specifications
External Components
The MK2771-15 requires a minimum number of external components for proper operation. Decoupling
capacitors of 0.01µF should be connected between VDD (or VDDIO) and GND on pins 5 and 24, 7 and
10, 22 and 19, and 21 and 18, as close to the MK2771-15 as possible. VDD on pin 8 can be connected
directly to the VDD on pin 21. A series termination resistor of 33
Ω
may be used for each clock
output.The 13.500 MHz crystal must be connected as close to the chip as possible. The crystal should be a
parallel mode, pullable, with load capacitance of 14 pF. Consult ICS/MicroClock for recommended
suppliers. See MAN05 for recommended layout of the chip and external components.
3
Revision 122899
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
MDS 2771-15 E
MK2771-15
VCXO and Set-Top Clock Source
Pullable Crystal Specifications
Frequency
Correlation (load) Capacitance
CO/C1
ESR
Operating Temperature
Initial Accuracey
Temperature plus Aging Stability
13.500000 MHz
14 pF
240 max
35
Ω
max
0 to 70 °C
±20 ppm
±50 ppm
Package Outline and Package Dimensions
(
For current dimensional specifications, see JEDEC Publication No. 95.)
28 pin SSOP
E1
E
D
A1
e
Ordering Information
Part/Order Number
MK2771-15R
MK2771-15RTR
Marking
MK2771-15R
MK2771-15R
Shipping packaging
tubes
tape and reel
c
b
A
L
Symbol
A
A1
b
c
D
e
E
E1
L
Inches
Min
Max
0.053 0.069
0.004 0.010
0.008 0.012
0.007 0.010
0.386 0.394
.025 BSC
0.228 0.244
0.150 0.157
0.016 0.050
Millimeters
Min
Max
1.35
1.75
0.102
0.254
0.203
0.305
0.191
0.254
9.804 10.008
0.635 BSC
5.791
6.198
3.810
3.988
0.406
1.270
Package
Temperature
28 pin SSOP (QSOP)
0-70 °C
28 pin SSOP (QSOP)
0-70 °C
While the information presented herein has been checked for both accuracy and reliability, Integrated Circuit Systems (ICS) assumes no responsibility for either its use or for the
infringement of any patents or other rights of third parties, which would result from its use. No other circuits, patents, or licenses are implied. This product is intended for use in
normal commercial applications. Any other applications such as those requiring extended temperature range, high reliability, or other extraordinary environmental requirements
are not recommended without additional processing by ICS. ICS reserves the right to change any circuitry or specifications without notice. ICS does not authorize or warrant any
ICS product for use in life support devices or critical medical instruments.
4
Revision 122899
Printed 11/16/00
Integrated Circuit Systems, Inc.• 525 Race Street • San Jose • CA • 95126 •(408) 295-9800tel• www.icst.com
Logic analyzers are widely used tools in digital design verification and debugging. They can verify the proper functioning of digital circuits and help users identify and troubleshoot faults. They ...[详细]
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