LPC3220/30/40/50
16/32-bit ARM microcontrollers; hardware floating-point
coprocessor, USB On-The-Go, and EMC memory interface
Rev. 2.1 — 24 June 2014
Product data sheet
1. General description
The LPC3220/30/40/50 embedded microcontrollers were designed for low power, high
performance applications. NXP achieved their performance goals using a 90 nanometer
process to implement an ARM926EJ-S CPU core with a vector floating point co-processor
and a large set of standard peripherals including USB On-The-Go. The
LPC3220/30/40/50 operates at CPU frequencies of up to 266 MHz.
The NXP implementation uses a ARM926EJ-S CPU core with a Harvard architecture,
5-stage pipeline, and an integral Memory Management Unit (MMU). The MMU provides
the virtual memory capabilities needed to support the multi-programming demands of
modern operating systems. The ARM926EJ-S also has a hardware based set of DSP
instruction extensions, which includes single cycle MAC operations, and hardware based
native Jazelle Java Byte-code execution. The NXP implementation has a 32 kB
instruction cache and a 32 kB data cache.
For low power consumption, the LPC3220/30/40/50 takes advantage of NXP’s advanced
technology development to optimize intrinsic power and uses software controlled
architectural enhancements to optimize application based power management.
The LPC3220/30/40/50 also includes 256 kB of on-chip static RAM, a NAND flash
interface, an Ethernet MAC, an LCD controller that supports STN and TFT panels, and an
external bus interface that supports SDR and DDR SDRAM as well as static devices. In
addition, the LPC3220/30/40/50 includes a USB 2.0 full-speed interface, seven UARTs,
two I
2
C-bus interfaces, two SPI/SSP ports, two I
2
S-bus interfaces, two single output
PWMs, a motor control PWM, six general purpose timers with capture inputs and compare
outputs, a Secure Digital (SD) interface, and a 10-bit Analog-to-Digital Converter (ADC)
with a touch screen sense option.
For additional documentation, see
Section 15 “References”.
2. Features and benefits
ARM926EJ-S processor, running at CPU clock speeds up to 266 MHz.
Vector Floating Point (VFP) coprocessor.
32 kB instruction cache and 32 kB data cache.
Up to 256 kB of Internal SRAM (IRAM).
Selectable boot-up from various external devices: NAND flash, SPI memory, USB,
UART, or static memory.
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Multi-layer AHB system that provides a separate bus for each AHB master, including
both an instruction and data bus for the CPU, two data busses for the DMA controller,
and another bus for the USB controller, one for the LCD, and a final one for the
Ethernet MAC. There are no arbitration delays in the system unless two masters
attempt to access the same slave at the same time.
External memory controller for DDR and SDR SDRAM as well as for static devices.
Two NAND flash controllers: One for single-level NAND flash devices and the other for
multi-level NAND flash devices.
Master Interrupt Controller (MIC) and two Slave Interrupt Controllers (SIC), supporting
74 interrupt sources.
Eight channel General Purpose DMA (GPDMA) controller on the AHB that can be
used with the SD card port, the high-speed UARTs, I
2
S-bus interfaces, and SPI
interfaces, as well as memory-to-memory transfers.
Serial interfaces:
10/100 Ethernet MAC with dedicated DMA Controller.
USB interface supporting either device, host (OHCI compliant), or On-The-Go
(OTG) with an integral DMA controller and dedicated PLL to generate the required
48 MHz USB clock.
Four standard UARTs with fractional baud rate generation and 64 byte FIFOs. One
of the standard UARTs supports IrDA.
Three additional high-speed UARTs intended for on-board communications that
support baud rates up to 921 600 when using a 13 MHz main oscillator. All
high-speed UARTs provide 64 byte FIFOs.
Two SPI controllers.
Two SSP controllers.
Two I
2
C-bus interfaces with standard open-drain pins. The I
2
C-bus interfaces
support single master, slave, and multi-master I
2
C-bus configurations.
Two I
2
S-bus interfaces, each with separate input and output channels. Each
channel can be operated independently on three pins, or both input and output
channels can be used with only four pins and a shared clock.
Additional peripherals:
LCD controller supporting both STN and TFT panels, with dedicated DMA
controller. Programmable display resolution up to 1024
768.
Secure Digital (SD) memory card interface, which conforms to the
SD Memory
Card Specification Version 1.01.
General Purpose (GP) input, output, and I/O pins. Includes 12 GP input pins, 24
GP output pins, and 51 GP I/O pins.
10-bit, 400 kHz Analog-to-Digital Converter (ADC) with input multiplexing from
three pins. Optionally, the ADC can operate as a touch screen controller.
Real-Time Clock (RTC) with separate power pin and dedicated 32 kHz oscillator.
NXP implemented the RTC in an independent on-chip power domain so it can
remain active while the rest of the chip is not powered. The RTC also includes a
32-byte scratch pad memory.
32-bit general purpose high-speed timer with a 16-bit pre-scaler. This timer
includes one external capture input pin and a capture connection to the RTC clock.
Interrupts may be generated using three match registers.
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.1 — 24 June 2014
2 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
Six enhanced timer/counters which are architecturally identical except for the
peripheral base address. Two capture inputs and two match outputs are pinned out
to four timers. Timer 1 brings out a third match output, timers 2 and 3 bring out all
four match outputs, timer 4 has one match output, and timer 5 has no inputs or
outputs.
32-bit millisecond timer driven from the RTC clock. This timer can generate
interrupts using two match registers.
WatchDog timer clocked by the peripheral clock.
Two single-output PWM blocks.
Motor control PWM.
Keyboard scanner function allows automatic scanning of an up to 8
8 key matrix.
Up to 18 external interrupts.
Standard ARM test/debug interface for compatibility with existing tools.
Emulation Trace Buffer (ETB) with 2048
24 bit RAM allows trace via JTAG.
Stop mode saves power while allowing many peripheral functions to restart CPU
activity.
On-chip crystal oscillator.
An on-chip PLL allows CPU operation up to the maximum CPU rate without the
requirement for a high frequency crystal. Another PLL allows operation from the
32 kHz RTC clock rather than the external crystal.
Boundary scan for simplified board testing.
User-accessible unique serial ID number for each chip.
TFBGA296 package with a 15 mm
15 mm
0.7 mm body.
3. Applications
Consumer
Medical
Industrial
Network control
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.1 — 24 June 2014
3 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
4. Ordering information
Table 1.
Ordering information
Package
Name
LPC3220FET296/01
[2]
LPC3230FET296/01
[2]
LPC3240FET296/01
[2]
LPC3250FET296/01
[2]
[1]
[2]
Type number
[1]
Description
Version
TFBGA296
TFBGA296
TFBGA296
TFBGA296
plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
plastic thin fine-pitch ball grid array package; 296 balls SOT1048-1
F =
40 C
to +85
C
temperature range. Note that Revision “A” parts with and without the /01 suffix are identical. For example,
LPC3220FET296 Revision “A” is identical to LPC3220FET296/01 Revision “A”.
Available starting with Revision “A”.
4.1 Ordering options
Table 2.
Part options
SRAM (kB)
128
256
256
256
10/100 Ethernet
0
0
1
1
LCD
controller
0
1
0
1
Temperature range (C)
40
to +85
40
to +85
40
to +85
40
to +85
Package
TFBGA296
TFBGA296
TFBGA296
TFBGA296
Type number
LPC3220FET296/01
LPC3230FET296/01
LPC3240FET296/01
LPC3250FET296/01
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.1 — 24 June 2014
4 of 80
NXP Semiconductors
LPC3220/30/40/50
16/32-bit ARM microcontrollers
5. Block diagram
ethernet
PHY
interface
USB
transceiver
interface
LCD
panel
interface
32-bit wide
external
memory
ETHERNET
10/100
MAC
4
VFP9
ETB
ETM 9
D-CACHE
32 kB
D-SIDE
CONTROLLER
ARM
9EJS
MMU
I-CACHE
32 kB
I-SIDE
CONTROLLER
INSTRUCTION
1
DMA
CONTROLLER
M0
2
M1
3
5
6
USB OTG
CONTROLLER
LCD
CONTROLLER
DATA
master layer
slave port
0
1
2
3
0
EXTERNAL
MEMORY
CONTROLLER
port 3
port 4
port 0
5
AHB slaves
SLC
NAND
6
DMA
MLC
NAND
AHB
APB slaves
TO
APB
BRIDGE
SPI
×
2
SRAM
256 kB
ROM
16 kB
SD
CARD
SSP
×
2
I2S
×
2
USB
SDRAM
ETB
ETHERNET
LCD
register interfaces
7
32-bit AHB matrix
AHB
APB slaves
TO
APB
BRIDGE
I2C
×
2
STANDARD
UART
×
4
MOTOR
CONTROL PWM
= Master/Slave connection supported
by the multilayer AHB matrix
WATCHDOG
TIMER
AHB
FAB slaves
TO
APB
BRIDGE
SYSTEM
CONTROL
TIMERS
×
6
PWM
×
2
RTC
GPIO
INTERRUPT
CONTROL
DEBUG
KEY
SCANNER
HS UART
×
3
UART
CONTROL
10-BIT
ADC/TS
002aae397
Fig 1.
Block diagram of LPC3220/30/40/50
LPC3220_30_40_50
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2014. All rights reserved.
Product data sheet
Rev. 2.1 — 24 June 2014
5 of 80
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