Operating Temperature Range ........................... -40NC to +85NC
Junction Temperature ......................................................+150NC
Storage Temperature Range ............................ -65NC to +150NC
Lead Temperature (soldering, 10s) ................................. +300NC
Soldering Temperature (reflow) .......................................+260NC
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation
of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum
rating conditions for extended periods may affect device reliability.
Package Thermal Characteristics
(Note 1)
TDFN
Junction-to-Ambient Thermal Resistance (q
JA
).......59.3NC/W
Junction-to-Case Thermal Resistance (q
JC
) ...........22.5NC/W
Note 1:
Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to
www.maximintegrated.com/thermal-tutorial.
Electrical Characteristics
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz or 250kHz, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
ANALOG INPUT (Note 3)
Input Voltage Range
AIN+ to AIN-, K =
AIN+ to GND
AIN- to GND
Input Leakage Current
Input Capacitance
Input-Clamp Protection Current
DC ACCURACY (Note 4)
Resolution
No Missing Codes
Offset Error
Offset Temperature Coefficient
Gain Error
Gain Error Temperature
Coefficient
MAX11167, T
A
= T
MIN
to T
MAX
Integral Nonlinearity
INL
MAX11167, T
A
= +25°C to +85°C
MAX11166, T
A
= T
MIN
to T
MAX
MAX11166, T
A
= +25°C to +85°C
Differential Nonlinearity
Positive Full-Scale Error
www.maximintegrated.com
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
5.000
4.096
-K x V
REF
-(V
DD
+
0.1)
-0.1
-10
-20
16
16
-1.5
±0.1
±2.4
±2
±1
-2.0
-1.0
-2.4
-1.5
-0.5
±0.5
±0.5
±0.5
±0.5
±0.2
+K x V
REF
+(V
DD
+
0.1)
+0.1
V
Absolute Input Voltage Range
V
µA
pF
mA
Bits
Bits
Acquisition phase
Both inputs
N
+0.001
15
+10
+20
+1.5
±10
mV
µV/°C
LSB
ppm/°C
+2.0
+1.0
+2.4
+1.5
+0.5
±14
LSB
LSB
LSB
DNL
Maxim Integrated
│
2
MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz or 250kHz, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
Negative Full-Scale Error
Analog Input CMRR
Power-Supply Rejection (Note 5)
Transition Noise
REFERENCE (Note 7)
REF Output Initial Accuracy
REF Output Temperature
Coefficient
REFIO Output Initial Accuracy
REFIO Output Temperature
Coefficient
REFIO Output Impedance
REFIO Input Voltage Range
Reference Buffer Initial Offset
Reference Buffer Temperature
Coefficient
External Compensation Capacitor
REF Voltage Input Range
REF Input Capacitance
REF Load Current
AC ACCURACY (Note 6)
VREF = 4.096V, reference
mode 3
Signal-to-Noise Ratio (Note 7)
SNR
fIN = 10kHz
VREF = 4.096V, reference
mode 1
VREF = 2.5V, reference
mode 3
Internal reference,
reference mode 0
VREF = 4.096V, reference
mode 3
Signal-to-Noise Plus Distortion
(Note 7)
SINAD
fIN = 10kHz
VREF = 4.096V, reference
mode 1
VREF = 2.5V, reference
mode 3
Internal reference,
reference mode 0
Spurious-Free Dynamic Range
Total Harmonic Distortion
Intermodulation Distortion (Note 8)
www.maximintegrated.com
SYMBOL
CMRR
PSR
CONDITIONS
MIN
TYP
-77
±3.0
0.5
MAX
±13
UNITS
LSB
dB
LSB
LSB
RMS
V
REF
TC
REF
V
REFIO
TC
REFIO
Reference mode 0
Reference mode 0
Reference modes 0 and 2
Reference modes 0 and 2
Reference modes 0 and 2
Reference mode 1
Reference mode 1
Reference mode 1
4.092
4.096
±9
4.100
±17
4.100
±15
4.25
+500
±10
V
ppm/°C
V
ppm/°C
kΩ
V
µV
µV/°C
µF
4.092
4.096
±6
10
3
-500
4.096
±6
C
EXT
V
REF
Required for reference modes 0 and 1,
recommended for reference modes 2 and 3
Reference modes 2 and 3
Reference modes 2 and 3
V
REF
= 4.096V,
reference modes 2
and 3
MAX11167, 250ksps
MAX11166, 500ksps
10
2.5
20
65
130
4.25
V
pF
µA
I
REF
91.5
92.6
92.4
dB
89.8
92.4
90
92.3
92.3
dB
89.5
91.8
SFDR
THD
IMD
96
105
-105
-115
-96
dB
dB
dB
Maxim Integrated
│
3
MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz or 250kHz, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
SAMPLING DYNAMICS
Throughput Sample Rate
Transient Response
Full-Power Bandwidth
Aperture Delay
Aperture Jitter
POWER SUPPLIES
Analog Supply Voltage
Interface Supply Voltage
Analog Supply Current
V
DD
Shutdown Current
V
OVDD
= 2.3V, MAX11167
Interface Supply Current (Note 9)
I
OVDD
V
OVDD
= 5.25V, MAX11167
V
OVDD
= 2.3V, MAX11166
V
OVDD
= 5.25V, MAX11166
OVDD Shutdown Current
V
DD
= 5V, V
OVDD
= 3.3V, MAX11167
reference mode = 2, 3
V
DD
= 5V, V
OVDD
= 3.3V, MAX11167
reference mode = 0, 1
V
DD
= 5V, V
OVDD
= 3.3V, MAX11166
reference mode = 2, 3
V
DD
= 5V, V
OVDD
= 3.3V, MAX11166
reference mode = 0, 1
DIGITAL INPUTS (DIN, SCLK, CNVST)
Input Voltage High
Input Voltage Low
Input Hysteresis
Input Capacitance
Input Current
DIGITAL OUTPUT (DOUT)
Output Voltage High
Output Voltage Low
Three-State Leakage Current
Three-State Output Capacitance
V
OH
V
OL
I
SOURCE
= 2mA
I
SINK
= 2mA
-10
15
V
OVDD
- 0.4
0.4
+10
V
V
µA
pF
V
IH
V
IL
V
HYS
C
IN
I
IN
V
IN
= 0V or V
OVDD
-10
0.7 x
V
OVDD
0.3 x V
OVDD
±0.05 x V
OVDD
10
+10
V
V
V
pF
µA
V
DD
V
OVDD
I
VDD
Internal reference mode
External reference mode
4.75
2.3
5.0
3.0
5.8
3.5
6.3
0.75
2.0
1.5
4.3
0.9
21.2
33.3
mW
26.4
40.5
5.25
5.25
6.5
4.0
10
0.85
2.4
2.0
5.0
10
µA
mA
V
V
mA
µA
MAX11166
MAX11167
Full-scale step
-3dB point
-0.1dB point
6
> 0.2
2.5
< 50
0.01
0.01
500
250
400
ksps
ns
MHz
ns
ps
RMS
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
Power Dissipation
www.maximintegrated.com
Maxim Integrated
│
4
MAX11166/MAX11167
16-Bit, 500ksps/250ksps, ±5V SAR ADCs
with Internal Reference in TDFN
Electrical Characteristics (continued)
(V
DD
= 4.75V to 5.25V, V
OVDD
= 2.3V to 5.25V, f
SAMPLE
= 500kHz or 250kHz, V
REF
= 4.096V; T
A
= T
MIN
to T
MAX
, unless otherwise
noted. Typical values are at T
A
= +25NC.) (Note 2)
PARAMETER
TIMING (Note 9)
Time Between Conversions
Conversion Time
Acquisition Time
CNVST Pulse Width
SCLK Period (CS Mode)
t
CYC
t
CONV
t
ACQ
t
CNVPW
t
SCLK
MAX11166
MAX11167
CNVST rising to
data available
t
ACQ
= t
CYC
- t
CONV
CS
mode
V
OVDD
> 4.5V
V
OVDD
> 2.7V
V
OVDD
> 2.3V
V
OVDD
> 4.5V
SCLK Period (Daisy-Chain Mode)
SCLK Low Time
SCLK High Time
SCLK Falling Edge to Data Valid
Delay
CNVST Low to DOUT D15 MSB
Valid (CS Mode)
CNVST High or Last SCLK
Falling Edge to DOUT High
Impedance
DIN Valid Setup Time from SCLK
Falling Edge
DIN Valid Hold Time from SCLK
Falling Edge
SCLK Valid Setup Time to
CNVST Falling Edge
SCLK Valid Hold Time to CNVST
Falling Edge
t
SCLK
t
SCLKL
t
SCLKH
V
OVDD
> 4.5V
t
DDO
V
OVDD
> 2.7V
V
OVDD
> 2.3V
t
EN
t
DIS
V
OVDD
> 2.7V
V
OVDD
< 2.7V
CS
Mode
V
OVDD
> 4.5V
t
SDINSCK
V
OVDD
> 2.7V
V
OVDD
> 2.3V
t
HDINSCK
t
SSCKCNF
t
HSCKCNF
3
5
6
0
3
6
ns
ns
ns
ns
V
OVDD
> 2.7V
V
OVDD
> 2.3V
MAX11166
MAX11167
MAX11166
MAX11167
2
4
1.35
2.7
0.5
1
5
14
20
26
16
24
30
5
5
12
18
23
14
17
20
ns
ns
ns
ns
ns
ns
100000
100000
1.5
3.0
µs
µs
µs
µs
ns
SYMBOL
CONDITIONS
MIN
TYP
MAX
UNITS
ns
Note 2:
Maximum and minimum limits are fully production tested over specified supply voltage range and at a temperature of +25°C
and +85°C. Limits below +25°C are guaranteed by design and device characterization. Typical values are not guaranteed.
Note 3:
See the
Analog Inputs
and
Overvoltage Input Clamps
sections.
Note 4:
See the
Definitions
section.
Note 5:
Defined as the change in positive full-scale code transition caused by a
stm32/stm8
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
