ispLever
CORE
TM
Gigabit Ethernet PCS IP Core for LatticeECP2M
User’s Guide
August 2007
ipug69_01.0
Lattice Semiconductor
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Introduction
The 1000BASE-X physical layer, also referred to as the Gigabit Ethernet (GbE) physical layer, consists of three
major blocks, the Physical Coding Sublayer (PCS), the Physical Medium Attachment sublayer (PMA), and the
Physical Medium Dependent sublayer (PMD). The LatticeECP2M™ embedded SERDES/PCS performs the PMA
function, and portions of the PMD and PCS functions, including link serialization/deserialization, code-group align-
ment, clock tolerance compensation buffering, and 8b10b encoding/decoding. However, the embedded SER-
DES/PCS does not provide all necessary functions for implementing a complete GbE physical layer solution. That’s
where the GbE PCS IP core comes in. The IP core provides the additional functions required to fully implement the
PCS functions of the GbE physical layer. These additional functions include a transmit state machine, a receive
state machine, and auto-negotiation.
This document describes the IP core’s operation and provides instructions for generating the core through
ispLEVER
®
IPexpress™, including instantiating, synthesizing, and simulating the core.
Features
• Implements the transmit, receive, and auto-negotiation functions of the IEEE 802.3z specification
• 8-bit GMII Interface operating at 125 MHz
• 8-bit Code-Group Interface operating at 125 MHz
• Parallel signal interface for control and status management
Functional Description
The GbE PCS IP core converts GMII data frames into 8-bit code groups in both transmit and receive directions;
and performs auto negotiation with a link partner as described in the IEEE 802.3z specification. The core’s block
diagram is shown in Figure 1. The following paragraphs detail the operation the IP core’s main functional blocks. An
example of how this IP core may be used in implementing a gigabit ethernet physical layer is shown in Figure 2.
Figure 1. GbE PCS IP Core Block Diagram
GMII Interface
RxD[7:0]
TxD[7:0]
Tx_CLK
Rx_Er
Tx_Er
MAC/PHY Mode
Rx _Clk
Rx_Dv
Tx_En
mr_adv_ability
mr_an_enable
mr_main_reset
mr_restart_an
Transmit
State Machine
Receive
State Machine
mr_an_complete
mr_lp_adv_ability
Auto-Negotiation
State Machine
Synchronization
State Machine
Rx_Err_Decode_Mode
mr_page_rx
Xmit_Autoneg
Signal_Detect
Tx_Data[7:0]
Rx_Data[7:0]
Correct_Disp
Rx_Disp_Err
Rx_Cv_Err
Tx_Kcntl
8-bit
Code Group Interface
2
Rx_Even
Rx_Kcntl
Lattice Semiconductor
Figure 2. Typical GbE Physical Layer Implementation
Gigabit Ethernet PCS IP Core
for LatticeECP2M
125 MHz
Ref Clk
Part of Embedded
SERDES/PCS
GMII
8 bits
@
125 MHz
User I/O
GMII
8 bits
@
125 MHz
GbE
PCS
IP Core
8BI
8 bits
@
125 MHz
8b10b
Encoder
Decoder
SERDES
Serial Interface
to Magnetics
or Backplane
Link State Machine
CML
Differential Pairs
@ 1.25 Gbps
Management
Interface
MDIO
Control
Registers
Transmit State Machine
The transmit state machine implements the transmit functions described in clause 36 of the IEEE 802.3 specifica-
tion. The state machine’s main purpose is to convert GMII data frames into code groups. A typical timing diagram
for this circuit block is shown below.
Note
that the state machine in this IP core does not fully implement the conver-
sion to 10-bit code groups as specified in the 802.3 specification. Instead, partial conversion to 8-bit code groups is
performed. A separate encoder (located in the LatticeECP2M embedded SERDES/PCS block) completes the full
conversion to 10-bit code groups.
Figure 3. Typical Transmit Timing Diagram
tx_en
tx_d
preamble SFD
Dest Add
Src Add
Len/Type
Data
FCS
tx_kcntl
tx_data
IDLE
SPD preamble SFD
Dest Add
Src Add
Len/Type
Data
FCS EPD IDLE
Synchronization State Machine
The synchronization state machine implements the alignment functions described in clause 36 of the IEEE 802.3
specification. The state machine’s main purpose is to determine whether incoming code groups are properly
aligned. Once alignment is attained, proper code groups are passed to the receive state machine. If alignment is
lost for an extended period, an auto negotiation restart is triggered.
Receive State Machine
The receive state machine implements the receive functions described in clause 36 of the IEEE 802.3 specifica-
tion. The state machine’s main purpose is to convert code groups into GMII data frames. A typical timing diagram
for this circuit block is shown below.
Note
that the state machine in this IP core does not fully implement the conver-
sion from 10-bit code groups as specified in the 802.3 specification. Instead, partial conversion from 8-bit code
groups is performed. A separate decoder (located in the LatticeECP2M embedded SERDES/PCS block) performs
10-bit to 8-bit conversions.
3
Lattice Semiconductor
Figure 4. Typical Receive Timing Diagram
rx_kcntl
rx_data
IDLE
SPD preamble SFD
Dest Add
Src Add
Len/Type
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Data
FCS EPD IDLE
rx_dv
rx_d
preamble SFD
Dest Add
Src Add
Len/Type
Data
FCS
Auto-Negotiation State Machine
The auto-negotiation state machine implements the link configuration functions described in clause 37 of IEEE
802.3 specification, including checking link readiness, determining duplex mode, and negotiating flow control. A
typical timing diagram is shown below.
Figure 5. Typical Auto-Negotiation Timing Diagram
power
up
reset
mr_page_rx
mr_an_complete
mr_adv_ability
mr_lp_adv_ability
0x0000
0x0020
0x4020
Signal Descriptions
Table 1. GbE PCS IP Core Input and Output Signals
Signal Name
Clock Signals
tx_clk_125
In
Transmit Clock
– 125 MHz clock source for transmit state machine. Incoming GMII
transmit data is sampled on rising edge of this clock. Outgoing 8-bit code group trans-
mit data is launched on the rising edge of this clock.
Receive Clock
– 125 MHz clock source for receive state machine and the synchroni-
zation state machine. Incoming signals are sampled on the rising edge of the clock.
Outgoing signals are launched on the rising edge of this clock.
Transmit Data
– Incoming GMII data.
Transmit Enable
– Active high signal, asserts when incoming data is valid.
Transmit Error
– Active high signal, used to denote transmission errors and carrier
extension on incoming GMII data port.
Receive Data
– Outgoing GMII data.
Receive Data Valid
– Active high signal, asserts when outgoing data is valid.
Receive Error
– Active high signal, used to denote transmission errors and carrier
extension on outgoing GMII data port.
8b
Transmit Data
– 8-bit code group data after passing through transmit state
machine.
8b
Transmit K Control
– Denotes whether current code group is data or control.
1=control 0=data
I/O
Description
rx_clk_125
GMII Signals
tx_d[7:0]
tx_en
tx_er
rx_d[7:0]
rx_dv
rx_er
8-Bit
Code Group Signals
tx_data[7:0]
tx_kcntl
In
In
In
In
Out
Out
Out
Out
Out
4
Lattice Semiconductor
Table 1. GbE PCS IP Core Input and Output Signals (Continued)
Signal Name
correct_disp
I/O
Out
Gigabit Ethernet PCS IP Core
for LatticeECP2M
Description
Corrects Disparity
– Asserted during inter-packet gaps to ensure that negative dispar-
ity IDLE ordered-sets are transmitted by the LatticeECP2M embedded SERDES /PCS.
1=correct disparity, 0=normal
Auto-negotiation Transmitting
– This signal asserts when the IP core’s auto negotia-
tion state machine is active. The signal is used by the LatticeECP2M embedded SER-
DES/PCS to occasionally insert idle ordered sets into its receive path (eight ordered
sets every 2048 clocks). This facilitates proper operation of the embedded clock toler-
ance compensation circuit. 1=autoneg is active, 0=autoneg is not active
8b
Receive Data
– 8-bit code group data presented to the receive state machine.
8b
Receive K Control
– Denotes whether current code group is data or control.
1=control 0=data
Receive Error Control Mode
– The embedded SERDES block of the LatticeECP2M
FPGAs has two modes of interpreting errors, decoded and normal. In decoded mode,
the three signals (
rx_even
,
rx_cv_err
,
rx_disp_err
) are used to decode 1-of-8 error
conditions. In decoded mode, the IP core responds to the following errors:
xmit_autoneg
Out
rx_data[7:0]
rx_kcntl
In
In
rx_err_decode_mode
In
100 = Coding Violation Error
111 = Disparity Error
All other error codes are ignored by the IP core. In normal mode, the three error signals
(
rx_even
,
rx_cv_err
,
rx_disp_err
) behave normally. The
rx_err_decode_mode
signal should be set high for decode mode, and low for normal mode.
rx_even
rx_cv_err
rx_disp_err
signal_detect
Management Signals
mr_adv_ability[15:0]
mr_an_enable
mr_main_reset
mr_restart_an
mr_an_complete
mr_lp_adv_ability[15:0]
mr_page_rx
Miscellaneous Signals
rst_n
debug_link_timer_short
In
In
In
In
Rx Even
– This signal is only used when error decoding mode is active. Otherwise, the
signal should be tied low.
Rx Coding Violation Error
– In normal mode, an active high signal denoting a coding
violation error in the receive data path. In decode mode, used to decode 1 of 8 error
conditions.
Rx Disparity Error
– In normal mode, an active high signal denoting a disparity error in
the receive data path. In decode mode, used to decode 1 of 8 error conditions.
Signal Detect
– Denotes status of GbE PCS RX physical link. 1=signal is good; 0=loss
of receive signal
Advertised Ability
– Configuration status transmitted by PCS during auto negotiation
process.
Auto Negotiation Enable
– Active high signal that enables auto negotiation state
machine to function.
Main Reset
– Active high signal that forces all PCS state machines to reset.
Auto Negotiation Restart
– Active high signal that forces auto negotiation process to
restart.
Auto Negotiation Complete
– Active high signal that indicates that the auto negotia-
tion process is completed.
Link Partner Advertised Ability
– Configuration status received from partner PCS
entity during the auto negotiating process. The bit definitions are the same as
described above for the
mr_adv_ability
port.
Auto Negotiation Page Received
– Active high signal that asserts while the auto
negotiation state machine is in the
Complete_Acknowledge
state.
Reset
– Active low global reset
Debug Link Timer Mode
– Active high signal that forces the auto negotiation link timer
to run much faster than normal. This mode is provided for debug purposes (e.g.,allow-
ing simulations to run through the auto negotiation process much faster that the nor-
mal).
In
In
In
In
Out
Out
Out
In
In
5
实时操作系统RTOS
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
