MK68564
SERIAL INPUT OUTPUT
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COMPATIBLE WITH MK68000 CPU
COMPATIBLE WITH MK68000 SERIES DMA’s
TWO INDEPENDENT FULL-DUPLEX CHAN-
NELS
TWO INDEPENDENT BAUD-RATE GENER-
ATORS
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Crystal oscillator input
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Single-phase TTL clock input
DIRECTLY ADDRESSABLE REGISTERS
(all control registers are read/write)
DATA RATE IN SYNCHRONOUS OR ASYN-
CHRONOUS MODES
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0-1.25M bits/second with 5.0MHz system
clock rate
SELF-TEST CAPABILITY
RECEIVE DATA REGISTERS ARE QUADRU-
PLY BUFFERED ; TRANSMIT REGISTERS
ARE DOUBLY BUFFERED
DAISY-CHAIN PRIORITY INTERRUPT LOGIC
PROVIDES AUTOMATIC INTERRUPT VECTO-
RING WITHOUT EXTERNAL LOGIC
MODEM STATUS CAN BE MONITORED
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Separate modem controls for each channel
ASYNCHRONOUS FEATURES
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5, 6, 7, or 8 bits/character
or 2 stop
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1, 1
1/2
,odd, or no bits
parity
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Even,
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x1, x16, x32, and x64 clock modes
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Break generation and detection
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Parity, overrun, and framing error detection
BYTE SYNCHRONOUS FEATURES
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Internal or external character synchronization
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One or two sync characters in separate regis-
ters
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Automatic sync character insertion
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CDC-16 or CRC-CCITT block check genera-
tion and checking
BIT SYNCHRONOUS FEATURES
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Abort sequence generation and detection
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Automatic zero insertion and deletion
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Automatic flag insertion between messages
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Address field recognition
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I-field residue handling
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Valid receive messages protected from over-
run
CRC-16 or CRC-CCITT block check genera-
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tion and checking
1
PDIP48
(Plastic Package)
PLCC52
(Chip Carrier)
DESCRIPTION
The MK68564 SIO (Serial Input Output) is a dual-
channel, multi-function peripheral circuit, designed
to satisfy a wide variety of serial data communica-
tions requirements in microcomputer systems. Its
basic function is a serial-to-parallel, parallel-to-serial
converter/controller ; however within that role, it is
systems software configurable so that its ”persona-
lity” may be optimized for any given serial data
communications application.
The MK68564 is capable of handling asynchronous
protocols, synchronous byte-oriented protocols
(such as IBM Bisync), and synchronous bit-oriented
protocols (such as HDLC and IBM SDLC). This ver-
satile device can also be used to support virtually
any serial protocol for applications other than data
communications (cassette or floppy disk interface,
for example).
The MK68564 can generate and check CRC codes
in any synchronous mode and may be programmed
to check data integrity in various modes. The device
also has facilities for modem controls in each chan-
nel. In applications where these controls are not
needed, the modem controls may be used for gene-
ral-purpose I/O.
January 1989
1/46
MK68564
SIO PIN DESCRIPTION
GND :
V
CC
:
CS :
R/W :
DTACK :
Ground
+ 5 Volts (± 5%)
Chip Select (input, active low). CS is used to select the MK68564 SIO for accesses to
the internal registers. CS and IACK must not be asserted at the same time.
Read/write (input). R/W is the signal from the bus master, indicating wether the current
bus cycle is a Read (high) or Write (low) cycle.
Data Transfer Acknowledge (output, active low, three stateable). DTACK is used to
signal the bus master that data is ready or that data has been accepted by the
MK68564 SIO.
Address Bus (inputs). The address bus is used to select one of the internal registers
during a read or write cycle.
Data Bus (bidirectional, threee-stateable). The data bus is used to transfer data to or
from the internal registers during a read or write cycle. It is also used to pass a vector
during an interrupt acknowledge cycle.
Clock (input). This input is used to provide the internal timing for the MK68564 SIO.
Device Reset (input, active low). RESET disables both receivers and transmitters, forces
TxDA and TxDB to a marking condition, forces the modem controls high and disables
all interrupts. With the exception of the status registers, data registers, and the vector
register, all internal registers are cleared. The vector register is reset to ”0FH”.
Interrupt Request (output, active low, open drain). INTR is asserted when the MK68564
SIO is requesting an interrupt. INTR is negated during an interrupt acknowledge cycle
or by clearing the pending interrupt(s) through software.
Interrupt acknowledge (input, active low). IACK is used to signal the MK68564 SIO that
the CPU is acknowledging an interrupt. CS and IACK must not be asserted at the same
time.
Interrupt Enable In (input, active low). IEI is used to signal the MK68564 SIO that no
higher priority device is requesting interrupt service.
Interrupt Enable Out (output, active low). IEO is used to signal lower priority peripherals
that neither the MK68564 SIO nor another higher priority peripheral is requesting
interrupt service.
Baud Rate Generator inputs. A crystal may be connected between XTAL1 and XTAL2,
or XTAL1 may be driven with a TTL level clock. When using a crystal, external
capacitors must be connectd. When driving XTAL1 with a TTL level clock, XTAL2 must
be allowed to float.
Receiver Ready (outputs, active low). Programmable DMA output for the receiver. The
RxRDY pins pulse low when a character is available in the receive buffer.
Transmitter Ready (outputs, active low). Programmable DMA output for the transmitter.
The TxRDY pins pulse low when the transmit buffer is empty.
Clear to Send (inputs, active low). If Tx Auto Enables is selected, these inputs enable
the transmitter of their respective channels. If Tx Auto Enables is not selected, these
inputs may be used as general purpose input pins. The inputs are Scmit-trigger
buffered to allow slow rise-time input signals.
Data Carrier Detect (inputs, active low). If Rx Auto Enables is selected, these inputs
enable the receiver of their respective channels. If Rx Auto Enables is not selected,
these inputs may be used as general purpose input pins. The inputs are Schmit-trigger
buffered to allow slow rise-time input signals.
Receive Data (inputs, active high). Serial data input to the receiver.
Transmit Data (outputs, active high). Serial data output of the transmitter.
A1-A5 :
D0-D7
CLK :
RESET :
INTR :
IACK :
IEI :
IEO :
XTAL1, XTAL2 :
RxRDYA, RxRDYB:
TxRDYA, TxRDYB :
CTSA, CTSB :
DCDA, DCDB :
RxDA, RxDB :
TxDA, TxDB :
2/46
MK68564
SIO PIN DESCRIPTION
(continued)
RxCA, RxCB :
Receiver Clocks (input/output). Programmable pin, receive clock input, or baud rate
generator output. The inputs are Schmit-trigger buffered to allow slow rise-time input
signals.
Transmitter Clocks (input/output). Programmable pin, transmit clock input, or baud rate
generator output. The inputs are Schmit-trigger buffered to allow slow rise-time input
signals.
Request to Send (outputs, active low). These outputs follow the inverted state
programmed into the RTS bit. When the RTS bit is reset in the asynchronous mode, the
output will not change until the character in the transmitter is completely shifted out.
These pins may be used as general purpose outputs.
Data Terminal Ready (outputs, Active low). These outputs follow the inverted state
programmed into the DTR bit. These pins may also be used as general purpose
outputs.
Synchronization (input/output, active low). The SYNC pin is an output when Monosync,
Bisync, or SDLC mode is programmed. It is asserted when a sync/flag character is
detected by the receiver. The SYNC pin is a general purpose input in the Asynchronous
mode and an input to the receiver in the External Sync Mode.
TxCA, TxCB :
RTSA, RTSB :
DTRA, DTRB :
SYNCA, SYNCB :
Figure 1a
: Dual In Line Pin Configuration.
Figure 1b
: Chip Carrier Pin Configuration.
3/46
MK68564
SIO SYSTEM INTERFACE
INTRODUCTION
The MK68564 SIO is designed for simple and effi-
cient interface to a MK68000 CPU system. All data
transfers between the SIO and the CPU are asyn-
chronous to the system clock. The SIO system
timing is derived from the chip select input (CS) du-
ring normal read and write sequences, and from the
interrupt acknowledge input (IACK) during an ex-
ception processing sequence. CS is a function of
address decode and (normally) lower data strobe
(LDS). IACK is a function of the interrupt level on ad-
dress lines A1, A2, and A3, an interrupt acknow-
ledge function code (FC0-FC2), and LDS.
Note : CS and IACK can never be asserted at the
same time.
Note : Unused inputs should be pulled up or down,
but never left floating.
READ SEQUENCE
The SIO will begin a read cycle if, on the falling edge
of CS, the read-write (R/W) pin is high. The SIO will
respond by decoding the address bus (A1-A5) for
the register selected, by placing the contents of that
register on the data bus pins (D0-D7), and by driving
the data transfer acknowledge (DTACK) pin low. If
the register selected is not implemented on the SIO,
the data bus pins will be driven high, and then
DTACK will be asserted. When the CPU has acqui-
red the data, the CS signal is driven high, at which
time the SIO will drive DTACK high and then three-
state DTACK and D0-D7.
WRITE SEQUENCE
The SIO will begin a write cycle if, on the falling edge
of CS, the R/W pin is low. The SIO will respond by
latching the data bus, by decoding the address bus
for the register selected, by loading the register with
the contents of the data bus, and by driving DTACK
low. When the CPU has finished the cycle, the CS
input is driven high. At this time, the SIO will drive
DTACK high and will then three-state DTACK. If the
register selected is not implemented on the SIO, the
normal write sequence will proceed, but the data
bus contents will not be stored.
INTERRUPT SEQUENCE
The SIO is designed to operate as an independent,
interrupting peripheral, or, when interconnected
with other components, an interrupt priority daisy
chain can be formed.
Independent Operation.
Independent operation
requires that the interrupt enable in pin (IEI) be
connected to ground. The SIO starts the interrupt
sequence by driving the interrupt request pin (INTR)
low. The CPU responds to the interrupt by starting
an interrupt acknowledge cycle, in which the SIO
IACK pin is driven low. The highest priority interrupt
request in the SIO,at the time IACK goes low, places
its vector on the data bus pins. The SIO releases the
INTR pin and drives DTACK low. When the CPU has
acquired the vector, the IACK signal is driven high.
The SIO responds by driving DTACK to a high level
and then three-stating DTACK and D0-D7. If more
than one interrupt request is pending at the start of
an interrupt acknowledge sequence, the SIO will
drive the INTR pin low following the completion of
the interrupt acknowledge cycle. This sequence will
continue until all pending interrupts are cleared. If
the SIO is not requesting an interrupt when IACK
goes low, the SIO will not respond to the IACK signal
; DTACK and the data bus will remain three-stated.
Daisy Chain Operation.
The interrupt priority chain
is formed by connecting the interrupt enable out pin
(IEO) of a higher priority part to IEI of the next lower
priority part. The highest priority part in the chain
should have IEI tied to ground. The Daisy Chaining
capability (figures 2 and 3) requires that all parts in
a chain have a common IACK signal. When the
common IACK goes low, all parts freeze and priori-
tize interrupts in parallel. Then priority is passed
down the chain, via IEI and IEO, until a part which
has a pending interrupt, once IEI goes low, passes
a vector, does not propagate IEO, and generates
DTACK.
The state of the IEI pin does not affect the SIO in-
terrupt control logic. The SIO can generate an inter-
rupt request any time its interrupts are enabled. The
IEO pin is normally high ; it will only go low during
an IACK cycle if IEI is low and no interrupt is pending
in the SIO. The IEO pin will be forced high whenever
IACK or IEI goes high.
4/46
MK68564
Figure 2 :
Conceptual Circuit of the MK68564 SIO Daisy Chaining Logic.
V000376
Figure 3 :
Daisy Chaining.
V000377
Figure 4 :
DMA Interface Timing.
V000378
5/46
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