MK41T56
MKI41T56
512 bit (64b x8) Serial Access TIMEKEEPER
®
SRAM
COUNTERS for SECONDS, MINUTES,
HOURS, DAY, DATE, MONTH and YEARS
SOFTWARE CLOCK CALIBRATION
AUTOMATIC POWER-FAIL DETECT and
SWITCH CIRCUITRY
I
2
C BUS COMPATIBLE
56 BYTES of GENERAL PURPOSE RAM
ULTRA-LOW BATTERY SUPPLY CURRENT of
500nA
OPERATING TEMPERATURE:
– MK41T56: 0 to 70°C
– MKI41T56: –40 to 85°C
AUTOMATIC LEAP YEAR COMPENSATION
DESCRIPTION
The MK41T56 TIMEKEEPER
®
is a low power 512
bit static CMOS RAM organized as 64 words by 8
bits. A built-in 32.768 kHz oscillator (external crystal
controlled) and the first 8 bytes of the RAM are used
for the clock/calendar function and are configured
in binary coded decimal (BCD) format. Addresses
and data are transferred serially via a two-line
bi-directional bus. The built-in address register is
incremented automatically after each write or read
data byte. The MK41T56 clock has a built-in power
sense circuit which detects power failures and
automatically switches to the battery supply during
power failures. The energy needed to sustain the
RAM and clock operations can be supplied from a
small lithium button cell.
Table 1. Signal Names
OSCI
OCSO
FT/OUT
SDA
SCL
V
BAT
V
CC
V
SS
March 1999
Oscillator Input
Oscillator Output
Frequency Test / Output Driver
(Open Drain)
Serial Data Address Input / Output
Serial Clock
Battery Supply Voltage
Supply Voltage
Ground
1/15
8
1
PSDIP8 (N)
0.4mm Frame
8
1
SO8 (S)
150mil Width
Figure 1. Logic Diagram
VCC
VBAT
OSCI
SCL
MK41T56
MKI41T56
OSCO
SDA
FT/OUT
VSS
AI02304
MK41T56, MKI41T56
Figure 2A. DIP Pin Connections
Figure 2B. SOIC Pin Connections
MK41T56
MKI41T56
OSCI
OSCO
VBAT
VSS
1
2
3
4
8
7
6
5
AI02305
MK41T56
MKI41T56
VCC
FT/OUT
SCL
SDA
OSCI
OSCO
VBAT
VSS
1
2
3
4
8
7
6
5
AI02306
VCC
FT/OUT
SCL
SDA
Table 2. Absolute Maximum Ratings
Symbol
T
A
T
STG
V
IO
V
CC
I
O
P
D
Parameter
Ambient Operating Temperature
MK41T56
MKI41T56
Value
0 to 70
–40 to 85
–55 to 125
–0.3 to 7
–0.3 to 7
20
0.25
Unit
°C
°C
V
V
mA
W
Storage Temperature (V
CC
Off, Oscillator Off)
Input or Output Voltages
Supply Voltage
Output Current
Power Dissipation
Note:
Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress
rating only and functional operation of the device at these or any other conditions above those indicated in the operational section of
this specification is not implied. Exposure to the absolute maximum rating conditions for extended periods of time may affect
reliability.
CAUTION:
Negative undershoots below –0.3 volts are not allowed on any pin while in the Battery Back-up mode.
Table 3. Register Map
Address
D7
0
1
2
3
4
5
6
7
OUT
ST
X
X
X
X
X
X
X
X
X
D6
D5
10 Seconds
10 Minutes
10 Hours
X
X
X
Date
Month
Years
Calibration
D4
Data
D3
D2
D1
D0
Function/Range
BCD Format
Seconds
Minutes
Hour
Day
Date
Month
Year
Control
00-59
00-59
00-23
01-07
01-31
01-12
00-99
Seconds
Minutes
Hours
Day
10 Date
X
10 M.
10 Years
FT
S
Keys: S
= SIGN Bit;
FT
= FREQUENCY TEST Bit;
ST
= STOP Bit;
OUT
= Output level;
X
= Don’t care.
2/15
MK41T56, MKI41T56
Figure 3. Block Diagram
1 Hz
OSCI
OSCILLATOR
32.768 kHz
OSCO
FT/OUT
VCC
VSS
VBAT
VOLTAGE
SENSE
and
SWITCH
CIRCUITRY
DIVIDER
SECONDS
MINUTES
HOURS
DAY
DATE
MONTH
CONTROL
LOGIC
YEAR
CONTROL
SCL
SERIAL
BUS
INTERFACE
RAM
(56 x 8)
ADDRESS
REGISTER
SDA
AI00586C
DESCRIPTION
(cont’d)
Data retention time is in excess of 10 years with a
50mAh 3V lithium cell. The MK41T56 is supplied in
8 pin Plastic Dual-in-Line and 8 lead Plastic SOIC
packages.
OPERATION
The MK41T56 clock operates as a slave device on
the serial bus. Access is obtained by implementing
a start condition followed by the correct slave ad-
dress (11010000). The 64 bytes contained in the
device can then be accessed sequentially in the
following order:
1.
Seconds Register
2.
Minutes Register
3.
Hours Register
4.
Day Register
5.
Date Register
6.
Month Register
7.
Years Register
8.
Control Register
9 to 64. RAM
Table 4. AC Measurement Conditions
Input Rise and Fall Times
Input Pulse Voltages
Input and Output Timing Ref. Voltages
≤
5ns
0 to 3V
1.5V
Note that Output Hi-Z is defined as the point where data is no
longer driven.
Figure 4. AC Testing Load Circuit
5V
1.8kΩ
DEVICE
UNDER
TEST
1kΩ
OUT
CL = 100pF
CL includes JIG capacitance
AI01019
3/15
MK41T56, MKI41T56
Table 5. Capacitance
(1,2)
(T
A
= 25
°C,
f = 1 MHz )
Symbol
C
IN
C
OUT (2)
Parameter
Input Capacitance (SCL)
Output Capacitance (SDA, FT/OUT)
Min
Max
7
10
Unit
pF
pF
Notes:
1. Effective capacitance measured with power supply at 5V.
2. Sampled, not 100% tested.
3. Outputs deselected.
Table 6. DC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C; V
CC
= 4.5V to 5.5V)
Symbol
I
LI
I
LO
I
CC1
I
CC2
V
IL
V
IH
V
OL
V
BAT(1)
I
BAT
Parameter
Input Leakage Current
Output Leakage Current
Supply Current
Supply Current (Standby)
Input Low Voltage
Input High Voltage
Output Low Voltage
Battery Supply Voltage
Battery Supply Current
T
A
= 25°C, V
CC
= 0V,
Oscillator ON, V
BAT
= 3V
I
OL
= 5mA, V
CC
= 4.5V
2.6
3
450
–0.3
3
Test Condition
0V
≤
V
IN
≤
V
CC
0V
≤
V
OUT
≤
V
CC
SCL/SDA = V
CC
–0.3V
Min
Typ
Max
±10
±10
1
1
1.5
V
CC
+ 0.8
0.4
3.5
500
Unit
µA
µA
mA
mA
V
V
V
V
nA
Note:
1. The RAYOVAC BR1225 or equivalent is recommended as the battery supply.
Table 7. Power Down/Up Trip Points DC Characteristics
(1)
(T
A
= 0 to 70°C or –40 to 85°C)
Symbol
V
PFD
V
SO
Parameter
Power-fail Deselect Voltage
Battery Back-up Switchover Voltage
Min
1.2 V
BAT
Typ
1.25 V
BAT
V
BAT
Max
1.285 V
BAT
Unit
V
V
Note:
1. All voltages referenced to V
SS
.
Table 8. Crystal Electrical Characteristics
(Externally Supplied)
Symbol
f
O
R
S
C
L
Notes:
Parameter
Resonant Frequency
Series Resistance
Load Capacitance
Min
Typ
32.768
Max
Unit
kHz
35
12.5
kΩ
pF
Load capacitors are integrated within the MK41T56. Circuit board layout considerations for the 32.768 kHz crystal of
minimum trace lengths and isolation from RF generating signals should be taken into account.
STMicroelectronics recommends the ECS-.327-12.5-8SP-2 quartz crystal is recommended for industrial temperature operations.
ESC Inc. can be contacted at 800-237-1041 or 913-782-7787 for further information on this crystal type.
4/15
MK41T56, MKI41T56
Table 9. Power Down/Up Mode AC Characteristics
(T
A
= 0 to 70°C or –40 to 85°C)
Symbol
t
PD
t
FB
t
RB
t
REC
Parameter
SCL and SDA at V
IH
before Power Down
V
PFD
(min) to V
SO
V
CC
Fall Time
V
SO
to V
PFD
(min) V
CC
Rise Time
SCL and SDA at V
IH
after Power Up
Min
0
300
100
200
Max
Unit
ns
µs
µs
µs
Figure 5. Power Down/Up Mode AC Waveforms
VCC
VPFD
VSO
tPD
SDA
SCL
tFB
tRB
tREC
IBAT
DATA RETENTION TIME
AI00595
OPERATION
(cont’d)
The clock continually monitors V
CC
for an out of
tolerance condition. Should V
CC
fall below V
PFD
,
the device terminates an access in progress and
resets the device address counter. Inputs to the
device will not be recognized at this time to prevent
erroneous data from being written to the device
from an out of tolerance system. When V
CC
falls
below V
BAT
, the device automatically switches over
to the battery and powers down into an ultra low
current mode of operation to conserve battery life.
Upon power-up, the device switches from battery
to V
CC
at V
BAT
and recognizes inputs when V
CC
goes above V
PFD
volts.
2-WIRE BUS CHARACTERISTICS
This bus is intended for communication between
different ICs. It consists of two lines: one bi-direc-
tional for data signals (SDA) and one for clock
signals (SCL). Both the SDA and the SCL lines
must be connected to a positive supply voltage via
a pull-up resistor.
The following protocol has been defined:
– Data transfer may be initiated only when the
bus is not busy.
– During data transfer, the data line must remain
stable whenever the clock line is High.
– Changes in the data line while the clock line is
High will be interpreted as control signals.
5/15
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