MAX11253/MAX11254 Family
Evaluation Kit
Evaluates: MAX11253/MAX11254
General Description
The MAX11253/MAX11254 evaluation kit (EV kit) pro-
vides a proven design to evaluate the MAX11253/
MAX11254 family of 16-bit/24-bit, 6-channel, 64ksps,
integrated PGA delta-sigma ADCs. The EV kit includes
a graphical user interface (GUI) that provides communi-
cation from the target device to the PC. The EV kit can
operate in multiple modes:
1)
Standalone Mode:
in “standalone” mode, the EV
kit is connected to the PC via a USB cable and
performs a subset of the complete EV kit functions
with limitations for sample rate, sample size, and no
support for coherent sampling.
FPGA Mode:
in “FPGA” mode, the EV kit is
connected to an Avnet ZedBoard™ through a low-
pin-count FMC connector. ZedBoard features a
Xilinx
®
Zynq
®
-7000 SoC, which connects to the
PC through an Ethernet port, allowing the GUI to
perform different operations with full control over
mezzanine card functions. The EV kit with FPGA
platform performs the complete suite of evaluation
tests for the target IC.
User-Supplied SPI Mode:
In addition to the USB and
FMC interfaces, the EV kit provides a 12-pin Pmod™-
style header for user-supplied SPI interface to con-
nect the signals for SCLK, DIN, DOUT, and CNVST.
Features and Benefits
●
High-Speed USB Connector, FMC Connector, and
Pmod-Style Connector
●
8MHz SPI Clock Capability through FMC Connector
●
8MHz SPI Clock Capability in Standalone Mode
●
Various Sample Sizes and Sample Rates
●
Collects Up to 1 Million Samples
(with FPGA Platform)
●
Time Domain, Frequency Domain, and Histogram
Plotting
●
Sync In and Sync Out for Coherent Sampling
(with FPGA Platform)
●
On-Board Input Buffers: MAX9632 and MAX44205
(Fully Differential)
●
On-Board Voltage References
(MAX6126 and MAX6070)
●
Proven PCB Layout
●
Fully Assembled and Tested
●
Windows XP-, Windows 7-, and Windows
8.1-Compatible Software
Ordering Information
appears at end of data sheet.
Pmod is a trademark of Digilent Inc.
ZedBoard is a trademark of Avnet, Inc.
Xilinx and Zynq are registered trademarks and Xilinx is a regis-
tered service mark of Xilinx, Inc.
Windows and Windows XP are registered trademarks and reg-
istered service marks of Microsoft Corporation.
2)
3)
The EV kit includes Windows XP
®
, Windows
®
7, and
Windows 8.1-compatible software for exercising the fea-
tures of the IC. The EV kit GUI allows different sample
sizes, adjustable sampling rates, internal or external ref-
erence options, and graphing software that includes the
FFT and histogram of the sampled signals.
The ZedBoard accepts a +12V AC-DC wall adapter. The
EV kit can be powered by a local +12V supply. The EV kit
has on-board transformers and digital isolators to sepa-
rate the IC from the ZedBoard/on-board processor.
The MAX11253/MAX11254 EV kit comes installed with a
MAX11253ATJ+ or MAX11254ATJ+ in a 32-pin TQFN-EP
package.
19-7584; Rev 1; 5/15
MAX11253/MAX11254 Family
Evaluation Kit
MAX11253/11254 EV Kit Photo
Evaluates: MAX11253/MAX11254
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MAX11253/MAX11254 Family
Evaluation Kit
System Block Diagram
Evaluates: MAX11253/MAX11254
MAX11253/MAX11254 EV Kit Files
FILE
MAX11253_54EVKitSetupV1.0.exe
DECRIPTION
Application Program
(GUI)
ZedBoard firmware
(SD card to boot
Zynq)
Note:
In the following section(s), software-related items
are identified by bolding. Text in
bold
refers to items direct-
ly from the EV system software. Text in
bold and under-
line
refers to items from the Windows operating system.
Procedure
1)
Boot.bin
The EV kit is fully assembled and tested. Follow the steps
below to verify board operation:
Visit
http://www.maximintegrated.com/evkitsoft-
ware
to download the latest version of the EV kit soft-
ware, MAX11253_54EVKITSetupV1.0.zip. Save the
EV kit software to a temporary folder and uncompress
the ZIP file.
Install the EV kit software and USB driver on your
computer by running the MAX11253_54EVKitSetupV1.0.exe
program inside the temporary folder. The program
files are copied to your PC and icons are created in
the Windows
Start | Programs
menu. At the end of
the installation process the installer will launch the in-
staller for the FTDIChip CDM drivers.
Quick Start
Required Equipment
●
●
●
●
●
●
MAX11253/MAX11254 EV kit
+12V (500mA) power supply
Micro-USB cable
ZedBoard FPGA platform
(optional –
NOT INCLUDED
with EVKit)
Function generator (optional)
Windows XP, Windows 7, or Windows 8.1 PC with a
spare USB port
2)
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3
MAX11253/MAX11254 Family
Evaluation Kit
For Standalone mode:
1)
2)
3)
4)
Verify that all jumpers are in their default positions for
the EV kit board (Table
2).
Connect the PC to the EV kit using a micro-USB ca-
ble.
Connect the +12V adapter to the EV kit.
Start the EV kit software by opening its icon in the
Start | Programs
menu. The EV kit software appears
as shown in
Figure 1.
From the
Device
menu select
Standalone.
Verify that the lower left status bar indi-
cates the EV Kit hardware is
Connected.
Connect the Ethernet cable from the PC to the Zed-
Board and configure the Internet Protocol Version
4 (TCP/Ipv4) properties in the local area connec-
tion to IP address 192.168.1.2 and subnet Mask to
255.255.255.0.
Verify that the ZedBoard SD card contains the Boot.
bin file for the MAX11253/MAX11254 EV kit.
Connect the EV kit FMC connector to the ZedBoard
FMC connector. Gently press them together.
Verify that all jumpers are in their default positions for
the ZedBoard (Table
1)
and EV kit board (Table
2).
Connect the 12V power supply to the ZedBoard.
Leave the Zedboard powered off.
Enable the ZedBoard power supply by sliding SW8 to
ON and connect the +12V adapter to the EV kit.
7)
Evaluates: MAX11253/MAX11254
Start the EV kit software by opening its icon in the
Start | Programs
menu. The EV kit software appears
as shown in
Figure 1.
From the
Device
menu select
FPGA.
Verify that the lower left status bar indicates
the EV Kit hardware is
Connected.
Connect the positive terminal of the function genera-
tor to the AIN0D+ (TP1) test point on the EV kit. Con-
nect the negative terminal of the function generator to
the AIN0D- (TP2) test point on the EV kit.
Configure the signal source to generate a 100Hz,
1V
P-P
sinusoidal wave with +1V offset.
Turn on the function generator.
In the Device menu, choose either standalone or the
FPGA option. In the configuration group, select Chan-
nel 0 and click
Convert
in the serial interface menu.
Click on the Scope tab.
Check the
Remove DC Offset
checkbox to remove
the DC component of the sampled data.
Click the
Capture
button to start the data analysis.
The EV kit software appears as shown in
Figure 1.
Verify that the frequency, which is displayed on the
right, is approximately 100Hz. The scope image has
buttons in the upper right corner that allow zooming
in to detail.
For Either Standalone or FPGA Mode:
1)
2)
3)
4)
For FPGA mode
(when connected to a Zedboard):
1)
5)
6)
7)
8)
9)
2)
3)
4)
5)
6)
Table 1. ZedBoard Jumper Settings
JUMPER
J18
JP11
JP10
JP9
JP8
JP7
J12
J20
SW8
SHUNT POSITION
1-2
2-3
1-2
1-2
2-3
2-3
NA
NA
OFF
VDDIO set for 3.3V.
DESCIPTION
Boot from SD Card
SD Card installed
Connected to 12V wall adapter
ZedBoard power switch, OFF while connecting boards
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MAX11253/MAX11254 Family
Evaluation Kit
Evaluates: MAX11253/MAX11254
Table 2. MAX11253/MAX11254 Board Jumper Settings
HEADER
JUMPER
POSITION
1-2*
JMP1
1-3
1-4
J8
J10
Open*
1-2
1-2*
2-3
Open*
J11
1-2
2-3
J12
1-2*
2-3
1-2*
J13
2-3
Open*
J14
1-2
J15
Open*
1-2
1-2*
J16
2-3
1-2*
J17
2-3
J24
1-2*
2-3
1-2*
J31
3-4*
DESCRIPTION
Use MAX6126 3.0V as VREF
signal
Use MAX6070 3.0V as VREF
signal
Use MAX6070 1.8V as VREF
signal
Generate +3.3V for DVDD
Generate +2.0V for DVDD
Select +3.3V or +2.0V as DVDD
Select +1.8V as DVDD
U1 uses internal clock
External clock from FPGA
External clock from U10
Select +3.3V as AVDD
Select +1.8V as AVDD
Select AVSS as REFN
Select REFN_S from J1 as
REFN for external sense point
Use internal 1.8V subregulator if
DVDD ≥ 2.0V
Use DVDD for internal logic if
DVDD ≤ 2.0V
Use TP23 as GPIO1
Use external SYNC signal
Select REFP_F signal as REFP
input
Select REFP_S signal from J1
as REFP input
Use AGND as AVSS. Use this
setting if AVDD is +3.3V
Use -1.8V as AVSS. Use this
setting if AVDD is +1.8V
Use VREF as REFP_F
Use AVDD as REFP_F
Short AIN2.1- (J27, TP38) to
AGND and for U11 noninverting
configuration
Short AIN2.1+ (J28, TP39) to
AGND and for U11 inverting
configuration
J37
J36
5-6
7-8*
Open*
1-2
J38
Open*
1-2
J35
5-6
7-8*
1-2*
3-4
J34
3-4*
1-2*
3-4
1-2*
J33
3-4*
1-2*
J32
3-4*
HEADER
JUMPER
POSITION
1-2*
DESCRIPTION
Short AIN2.3- (J29, TP42) to
AGND and for U12 noninverting
configuration
Short AIN2.3+ (J30, TP43) to
AGND and for U12 inverting
configuration
Short AIN2.2- (TP40) to AGND
and for U13 noninverting
configuration
Short AIN2.2+ (TP41) to
AGND and for U13 inverting
configuration
Short AIN2.4- (TP44) to AGND
and for U14 noninverting
configuration
Short AIN2.4+ (TP45) to
AGND and for U14 inverting
configuration
Connect output of U11 to
inverting input of U13
Connect AIN2.2- (TP40) to
inverting input of U13
Connect output of U11 to
noninverting input of U13
Connect AIN2.2+ (TP41) to
noninverting input of U13
Connect output of U12 to
inverting input of U14
Connect AIN2.4- (TP44) to
inverting input of U14
Connect output of U12 to
noninverting input of U14
Connect AIN2.4+ (TP45) to
noninverting input of U14
No offset to U13 noninverting
input
Offset U13 output by VREF/2
No offset to U14 noninverting
input
Offset U14 output by VREF/2
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