MachXO3L Breakout Board Evaluation Kit
User Guide
January 2015
EB94_1.1
MachXO3L Breakout Board Evaluation Kit
Introduction
The MachXO3L Breakout Board Evaluation Kit focuses on providing an environment to evaluate high speed source
synchronous interfaces with the Lattice MachXO3L-2100 and MachXO3L-6900 products in both 49-ball WLCSP
and 256-ball caBGA packages respectively.
The MachXO3L Breakout Board contains two sections for development. The first section of the board features the
MachXO3L-2100 which is optimized for MIPI D-PHY receiver and MIPI D-PHY transmitter interfaces with up to four
data lanes and one clock lane each. The second section of the board features the MachXO3L-6900. This section
provides a flexible IO evaluation environment for MIPI D-PHY, SubLVDS, FPD-LINK, FPC-LINK as well as other
source synchronous type protocols. The IO of the MachXO3L-6900 provides eight high speed data and two high
speed clock interfaces in both transmit and receive directions. Connection to these interfaces is available through
SMAs for signal integrity and performance evaluation.
Evaluation Kit Contents
• MachXO3L Breakout Board
• Pre-loaded Demo
• Mini USB Cable
• QuickStart Guide
Figure 1. MachXO3L Breakout Board (Top Side)
Red LEDs (D5, D6, D7, D8) +
Tricolor LED (U8)
JTAG Chain Control Header (J50)
12V Supply
Source (J2)
MachXO3L-2100 (U9)
MachXO3L-2100 MIPI D-PHY
Output Connector (J49)
JTAG or USB Device
Programming
Power Regulators
5 V, 3.3 V, 2.5 V, 1.8 V, 1.2 V
MachXO3L-6900 PMOD (J47) and
General Purpose Connector (J16)
MachXO3L-6900 SMA Connectors
for Differential Output
MachXO3L-6900 SMA Connectors
for Differential Input
MachXO3L-6900 PMOD (J46) and
General Purpose Connector (J37)
MachXO3L-6900 (U7)
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MachXO3L Breakout Board Evaluation Kit
Figure 2. MachXO3L Breakout Board (Bottom Side)
MachXO3L-2000 MIPI D-PHY
Input Connector (J48)
Overview
The MachXO3L Breakout Board allows for multi-device testing and scalability by providing a larger MachXO3L-
6900 and a smaller MachXO3L-2100 device. The MachXO3L-6900 has two high speed clock and eight high speed
data inputs and outputs. By default these ports are configured for MIPI D-PHY IO support, but can be modified for
various IO options, such as LVDS, SubLVDS and CMOS. The MachXO3L-6900 also has four general purpose IO
headers, two of which have the ability to connect with Digilent PMOD interface boards. Additionally, the
MachXO3L-6900 device has the ability to control four general purpose LEDs and one tri-color RGB LED.
The MachXO3L-2100 is attached to two connectors providing four data and one clock lanes configured for MIPI D-
PHY going in to and out of the FPGA. The pinout for the MachXO3L-2100 is optimized for low cost and small form
factor by operating only off of 1.2 V and 3.3 V CMOS IO rails.
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MachXO3L Breakout Board Evaluation Kit
Figure 3. MachXO3L Breakout Board Functional Block Diagram
MIPI DSI Input Connector
MachXO3L-2100
MIPI DSI Output Connector
FTDI USB
Configuration
Controller
JTAG
Control
Header
Differential Input SMA’s
Pre-configured for MIPI D-PHY
General Purpose Header
RGB
LED
PMOD Header
MachXO3L-6900C
General Purpose Header
PMOD Header
LED
LED
LED
LED
Differential Output SMA’s
Pre-configured for MIPI D-PHY
MachXO3L Devices
The MachXO3L Breakout Board features both the MachXO3L-6900 in 256-ball caBGA package and the
MachXO3L-2100 in 49-ball WLCSP package. These devices feature 2100 and 6900 LUTs and 74 and 240 kbits of
embedded block RAM respectively. Both of these devices feature a variety of features and programmability. For
more information on the capabilities of each device see DS1047,
MachXO3 Family Data Sheet.
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MachXO3L Breakout Board Evaluation Kit
Connector Descriptions
Configuration
The MachXO3L-2100 and MachXO3L-6900 parts can be programmed via JTAG through USB port or standalone
JTAG header. The USB path uses a FT2232H FTDI part to convert USB to JTAG. The standalone JTAG header
can be used to program the devices using the Lattice Programming Cable. In order to use the stand alone JTAG
header R5, R6, R7 and R8 to remove the FTDI part from the JTAG chain.
Power can be supplied to the board via mini USB port, 12 V power supply, from a separate board through the J48
DSI input connector or any combination of the three.
Figure 4. Configuration Connectors
USB
+ Supply
J1 – JTAG Header
12 V Supply
(optional)
Pin
1
2
3
4
5
6
7
8
Function
3.3 V
TDO
TDI
NC
NC
TMS
GND
TCK
J50 – JTAG Chain Control Header
Pin
1
2
3
4
5
6
Function
MachXO3L 2100 TDO
FTDI TDO
FTDI TDO
MachXO3L 6900 TDI
FTDI/MachXO3L 2100 TDI
MachXO3L 6900 TDO
JTAG Chain Options
2100 only
2100 + 6900
6900 only
1
2
3
4
5
6
1
2
3
4
5
6
1
2
3
4
5
6
5
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