Table of Contents
Introduction ....................................................................................................................5
Supported Device Families ............................................................................................................................ 6
Core Versions ................................................................................................................................................. 6
Supported Interface ........................................................................................................................................ 6
Device Utilization and Performance ............................................................................................................... 6
Memory Requirements ................................................................................................................................... 8
Functional Block Descriptions .....................................................................................9
Interface Descriptions ................................................................................................. 11
Parameters on Core10100 ........................................................................................................................... 11
CSR Interface Signals .................................................................................................................................. 12
Other Interface Signals ................................................................................................................................ 14
Software Interface ........................................................................................................ 17
Register Maps .............................................................................................................................................. 17
Frame Data and Descriptors ........................................................................................................................ 30
Internal Operation ........................................................................................................................................ 40
Interface Timing ........................................................................................................... 53
Core10100—CSR Interface ......................................................................................................................... 53
Core10100—Data Interface ......................................................................................................................... 53
Core10100-RMII Interface ............................................................................................................................ 55
Clock and Reset Control .............................................................................................................................. 55
Timing Constraints ....................................................................................................................................... 56
Tool Flows .................................................................................................................... 57
Licensing ...................................................................................................................................................... 57
SmartDesign ................................................................................................................................................ 57
Testbench Operation and Modification...................................................................... 59
Testbench operation and modification ......................................................................................................... 59
System Operation ........................................................................................................ 61
Transmit and Receive Functional Timing Examples ................................................ 63
Transmit Examples ....................................................................................................................................... 63
Transmit Descriptor and Data Fetches ......................................................................................................... 65
List of Document Changes ......................................................................................... 73
Core10100 v5.1 Handbook
2
Table of Contents
Product Support........................................................................................................... 75
Customer Service ........................................................................................................................................ 75
Customer Technical Support Center ........................................................................................................... 75
Technical Support ........................................................................................................................................ 75
Website ........................................................................................................................................................ 75
Contacting the Customer Technical Support Center ................................................................................... 75
ITAR Technical Support .............................................................................................................................. 76
Core10100 v5.1 Handbook
3
Introduction
Core10100 is a high-speed media access control (MAC) Ethernet controller (Figure 1). It implements Carrier
Sense Multiple Access with Collision Detection (CSMA/CD) algorithms defined by IEEE 802.3 for MAC over
an Ethernet connection. Communication with an external host is implemented via a set of Control and Status
registers and the DMA controller for external shared RAM. For data transfers, Core10100 operates as a
DMA master. It automatically fetches from transmit data buffers and stores receive data buffers into external
RAM with minimum CPU intervention. Linked list management enables the use of various memory allocation
schemes. Internal RAMs are used as configurable FIFO memory blocks, and there are separate memory
blocks for transmit and receive processes. The core has a generic host-side interface that connects with
external CPUs. This host interface can be configured to work with 8-, 16-, or 32-bit data bus widths with big
or little-endian byte ordering.
Transmit Data
RAM
Data
Interface
Data
Controller
Transmit
Control
Transmit
RMII/MII
Receive
Control
Receive
RMII/MII
Control
Interface
Control and Status
Registers and Control
Logic
Receive Data
RAM
Address
RAM
Figure 1
Core10100 Block Diagram
Figure 2
shows a typical application using Core10100. Typical applications include local area network (LAN)
controllers; avionics full-duplex switched Ethernet (AFDX) controllers and embedded systems.
Figure 3
shows the primary blocks of Core10100.
Shared
RAM
CPU
(8-, 16-, or 32-bit)
Data interface bus
Core10100
Control interface bus
RMII/MII
Interface
PHY
Figure 2
Typical Core10100 Application
Core10100 v5.1 Handbook
5
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