NB6L295MNGEVB,
NB6L295MMNGEVB
NB6L295MNG/
NB6L295MMNG Evaluation
Board User's Manual
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EVAL BOARD USER’S MANUAL
Introduction and Board Description
The NB6L295M Evaluation Board was designed to
provide a flexible and convenient platform to quickly
evaluate, characterize and verify the operation and
performance of either the NB6L295MMNG (CML) or the
NB6L295MNG (LVPECL) Dual Channel Programmable
Delay.
This evaluation board manual contains:
•
Information on the NB6L295M Evaluation Board
•
Appropriate Lab Setup
•
Detailed Board Features
•
Bill of Materials
This manual should be used in conjunction with the device
datasheet NB6L295M/D or NB6L295/D which contains full
technical details on the device specifications and operation.
The NB6L295M Evaluation Board was also designed to
accommodate a custom QFN−24 socket. Therefore, some
external components were installed on the bottom side of the
board.
Board Features
•
SMA connectors are provided for 1) all high−speed
differential input & (CML or LVPECL) output signals
and 2) for external SDI & control signals access
Board Layout
The evaluation board is constructed in four layers. The top
layer is the primary trace layer and is made with polyimide
material. This layer provides a high−bandwidth 50
W
controlled trace impedance environment for the equal length
inputs and outputs. The second layer is a copper ground
plane.
Layer Stack
L1 Signal
−
“High and Low Speed”
L2 SMA Ground
L3 VCC (Device positive power supply) and DUTGND
(Device negative power supply)
L4 Signal
−
“Low Speed”
What measurements can you expect to make?
•
On board programmable SDI circuitry minimizing
cabling, or, external SDI accessed through SMA
connectors.
•
Convenient and compact board layout
•
2.5 V or 3.3 V single or split−power supply operation
(banana jack connectors for VCC, SMAGND and
DUTGND; Separate PLDVCC power supply for on
board PLD
•
CML or LVPECL differential output signals are
accessed via SMA connectors with provision for load
termination resistors
With this evaluation board, the following measurements
could be performed in single ended or differential modes of
operation.
•
Propagation and Programmed Delay
•
Output Rise and Fall Time
•
Frequency Performance
•
Jitter
•
VCMR
−
Common Mode Range
©
Semiconductor Components Industries, LLC, 2012
April, 2012− Rev. 3
1
Publication Order Number:
EVBUM2082/D
NB6L295MNGEVB, NB6L295MMNGEVB
TEST AND MEASUREMENT SETUP AND PROCEDURE
Basic Lab Equipment (or Equivalent)
•
Agilent Signal Generator #8133A for INx / INx,
•
•
•
•
Dual Power Supplies
external Clock or Data source
Tektronix TDS8000 Oscilloscope or Frequency Counter
Agilent #6624A DC Power Supply
Digital Voltmeter
Matched high−speed cables with SMA connectors
0V
+
−
+2.5 V
+
−
V
CC
DUTGND
SMAGND
Lab Setup
A typical lab setup for taking time domain measurements
in differential mode operation is shown in Figures 6 and 7.
The following steps should be followed for proper
equipment setup:
Step 1: Connect Power Supply
+2.5 V
The NB6L295M and NB6L295 have positive supply pins,
VCC, VCC0 and VCC1, and negative supply pins,
(DUT)GND. The SMAGND (V
TT
) terminal is the isolated
termination ground plane for the outputs, only, and is not to
be confused with the device ground pin, (DUT)GND.
Three power levels must be provided to the board, VCC,
DUTGND, and SMAGND. Connect a power supplies to
banana jack connectors for VCC, PLDVCC, DUTGND and
SMAGND, which are provided on the bottom of the board.
By−pass capacitors have been installed from VCC to
SMAGND and from DUTGND to SMAGND at the banana
jacks.
DUTGND = PLDGND, therefore, when device power
supply is 2.5 V or 3.3 V, PLDVCC = DUTVCC. The
exposed pad on the PCB for the QFN−24 package is
connected to DUTGND.
Figure 4. “Split” or Dual Power Supply Connections
for NB6L295M, CML Outputs
Table 1. NB6L295M, CML OUTPUTS OFFSET POWER
SUPPLY CONFIGURATIONS
Power Supply
Connector
Color
Yellow
Red
Black
Black
Device Pin
PLDVCC
VCC
SMAGND
DUTGND
“Spilt” Power Supply
PLDVCC = 0 V
V
CC
= 0 V
V
TT
= 0 V
DUTGND =
−2.5
V or
−3.3
V
Dual Power Supplies
Table 2. NB6L295, LVPECL OUTPUTS “SPLIT”
POWER SUPPLY CONFIGURATIONS
Power Supply
Connector
Color
Yellow
Red
Black
Black
2.0 V
+
−
+1.3 V
+
−
Device Pin
PLDVCC
“Spilt” Power Supply
PLDVCC = +2.0 V
V
CC
= +2.0 V
V
TT
= 0 V
DUTGND =
−0.5
V or
−1.3
V
V
CC
DUTGND
SMAGND
VCC
SMAGND
DUTGND
+3.3 V
Figure 5. “Split” or Dual Power Supply Connections
for NB6L295, LVPECL Outputs
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4
NB6L295MNGEVB, NB6L295MMNGEVB
Step 2: CML & LVPECL Output Load Termination
NB6L295M
−
CML Outputs
(see Figures 4 and 7)
Step 4: Program the SDI
The CML Qx and Qx outputs must be externally DC
loaded and AC terminated. A “split” or dual power supply
technique can be used to take advantage of terminating the
CML outputs into 50
W
to Ground of an oscilloscope or a
frequency counter. Since V
TT
= V
CC
, offsetting V
CC
to 0 V
yields V
TT
= 0 V or Ground (SMAGND).
NB6L295
−
LVPECL Outputs
(see Figures 5 and 6)
The LVPECL Qx and Qx outputs have standard, open
emitter outputs and must be externally DC loaded and AC
terminated.
Taking advantage of the internal 50
W
to ground of the test
equipment, a split power supply technique will assure the
equal output loading and termination of both outputs.
Connect the Qx and Qx outputs of the device to the
oscilloscope with equally matched cables. Both outputs
must be equally loaded and terminated. The outputs are now
DC loaded and AC terminated with 50
W
to V
TT
, which is
the Ground internal to the oscilloscope. Since V
TT
= V
CC
−
2 V, offsetting V
CC
to +2.0 V yields V
TT
= 0 V or Ground
(SMAGND).
The V
TT
terminal connects to the isolated SMAGND
connector ground plane, and is not to be confused with the
device ground pin, DUTGND.
NOTE: When a single−ended output is being used, the
unconnected output for the pair
must be
terminated to V
TT
through a 50
W
resistor for
best operation. Unused output pairs may be left
unconnected. Since V
TT
= 0 V, a standard 50
W
SMA termination plug can be used.
Step 3: Connect and Setup Inputs
Set the signal generator amplitude to appropriate logic levels
For Clock, set the generator output for a square wave clock
signal with a 50% duty cycle.
For Differential Mode
Connect the differential outputs of the generator with
equally matched cables to the differential inputs of the
device (INx and INx). The differential inputs of the
NB6L295 incorporate internal 50
W
termination resistors.
For Single−Ended Mode
Connect the single−ended output of the generator to the
INx input of the device. V
th
must be applied to the
complementary input (INx) when operating in single−ended
mode. Refer to the device datasheet for details on
single−ended operation.
The VTx and VTx termination pins each have a trace from
package pin to a node where it can be connected to either
VCC, DUTGND or SMAGND, depending on the user’s
need.
The internal delay registers of the NB6L295/NB6L295M
may be programmed by a) the onboard PLD or b) by using
the three−lines for an external Serial Data Interface (SDI)
consisting of a SERIAL DATA (SDATA) input, a SERIAL
CLOCK (SCLK) input, and a SERIAL LOAD (SLOAD) as
follows:
a)
Onboard PLD
When using the onboard PLD for the SDI source,
1. Install the three jumpers located at J4
2. Insure PLDVCC power is applied
3. The 11−bit switches will program the NB6L295’s
11−bit shift register. Set SW2 and SW4 switches to
the desired values for the 11−bit word
4. Load the program values by depressing
momentary switch SW3, or send a pulse signal
(125 ns min) through J1.
Refer to the NB6L295 datasheet for details on the proper
settings for these switches.
b.
External SDI
An external SDI source can also program the
NB6L295/NB6L295M. See datasheet DC Table, AC Table,
as well as Figures 7 and 8. When using an external SDI
source, remove the three jumpers at J4.
To use the SDI ports, generate input SCLK, SDATA, and
SLOAD signals via the appropriate SMA connectors with
OFFSET LVCMOS/LVTTL LEVELS, i.e. +2.0 V HIGH
and
−1.3
V LOW for a 3.3 V LVPECL power supply. The
SCLK signal will sample the information presented on
SDATA line. Values are loaded and indexed into a 11−bit
shift register. The register shifts once per rising edge of the
SCLK input. The serial input SDATA bits must each meet
setup and hold timing to the respective SCLK rising edge as
specified in the AC Characteristics section of the datasheet
document. The LEAST Significant Bit (LSB), PSEL, is
indexed in first followed by MSEL and D0, D1, D2, D3, D4,
D5, D6, and D7, through MOST Significant Bit (MSB), D8,
indexed in last. A Pulse on the SLOAD pin after the SHIFT
register is fully indexed (11 clocks) will load and latch the
data values for the internal registers.
The SLOAD pulse Low to HIGH rising edge transition
transfers the data from the SHIFT register to the LATCH
register. The SLOAD Pulse HIGH to LOW transition will
lock the new data values into the LATCH register.
After the PLD programs the NB6L295/NB6L295M,
PLDVCC can be disconnected.
Input/Output Enable
−EN:
When switch SW1 is in the UP
position or is externally connected to a LOW through J15
SMA connector, the outputs are ENABLED.
To monitor the Qx and Qx outputs on an oscilloscope or
frequency counter:
•
The power supply needs to be DC offset
•
Assure that the instrument has internal 50
W
termination impedance to ground
•
Ensure the oscilloscope is triggered properly
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