UA5M15MP
5 - 18GHz Surface Mount Amplifier
with Integrated Bias
Features
• Wide operating range: 5-18GHz
• 3.3V, 100mA drain bias (gate N/C)
for gain and NF:
▪ 13 ±0.4dB gain, 7dB NF, 16dBm
Psat, 13.5dBm P1dB
• 5V, 130mA drain bias (gate N/C)
for power:
▪ 12.5 ±0.7dB gain, 9dB NF,
19.5dBm Psat, 17dBm P1dB
• Single supply voltage with
self-biasing gate OR direct control
of both gate and drain stages
Application
The UA5M15MP is ideally suited for:
• Point-to-point and point-to-multipoint
digital radio
• Spread spectrum broadband com-
munications
• LO driver or mixer isolation amplifier
• General isolation and gain block
amplifier
Description
The UA5M15MP is a two-stage pHEMT
amplifier MMIC in a Pb-free leadless plastic
QFN package. The IC features a positive
gain slope that offsets package loss, resulting
in a SMT part with excellent gain flatness
across a broad bandwidth. The device
can be operated at 5V 130mA for power
applications, or 3.3V 100mA for low-noise
and gain.
Surface Mount Package
•
•
16-pin Pb-free SMT QFN package
3x3mm pkg size; 0.5mm pad pitch
Functional Diagram
Key Characteristics:
Specifications pertain to wafer measurements with RF probes and DC bias
cards @ 25°C Vd=Vd1=Vd2, Vg=Vg1=Vg2, Id=Id1+Id2, Zo=50Ω
Frequency Range: 5 - 18GHz
Parameter
S21 (dB)
Flatness (±dB)
S11 (dB)
S22 (dB)
S12 (dB)
P1dB (dBm)
Psat (dBm)
NF (dB)
Description
Small Signal Gain
Gain Flatness
Input Match
Output Match
Reverse Isolation
1dB Compressed Output Power
Saturated Output Power
Noise Figure
Gain Bias: Vd=3.3V,
Vg=N/C, Id=100mA
Min
-
-
-
-
-
-
-
-
Typ
13
0.4
-14
-11
-35
13.5
16
7
Max
-
-
-
-
-
-
-
-
Power Bias: Vd=5V
Vg=N/C, Id=130mA
Min
-
-
-
-
-
-
-
-
Typ
12.5
0.7
-14
-11
-35
17
19.5
9
Max
-
-
-
-
-
-
-
-
SMD-00106 Rev C
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UA5M15MP
Typical Probed Performance QFN Package
S21
S11, S22
S12
Group Delay
SMD-00106 Rev C
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UA5M15MP
Supplemental Tested in Evaluation Fixture
S21
Output Power
S11, S22
Noise Figure
S12
Group Delay
SMD-00106 Rev C
Subject to Change Without Notice
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UA5M15MP
Table 1: Supplemental Specifications
Parameter
Vd1
Id1
Vd2
Id2
Vgg1
Vgg2
P
in
P
dc
T
ch
Θ
ch
Description
Drain Bias Voltage FET1
Drain Bias Current FET1
Drain Bias Voltage FET1
Drain Bias Current FET1
Drain Bias Current FET1
Drain Bias Current FET1
Input Power (CW)
Power Dissipation
Channel Temperature
Thermal Resistance (T
case
=85˚C)
Min
-
-
-
-
-4
-4
-
-
-
-
Typ
3.3V, 5V
-
3.3V, 5V
-
N/C
N/C
-
0.33W, 0.65W
-
60˚C/W
Max
6V
90mA
6V
110mA
+1V
+1V
12dBm
-
150˚C
-
150˚C
Caution, ESD
Sensitive Device
T
STORAGE
Storage Temperature
1
-65˚C
-
1
Passed temperature cyling per JESD22-A104C, -65°C to +150°C, 250 cycles, dwells of 1
minute, 10°C/minute minimum ramp rate.
Functional Block Diagram
Table 2: Typical Bias Values
Vdd (V)
+5.0
+4.0
+3.3
+2.5
Idd (mA)
130
110
100
79
App
Power
-
Gain
Low-noise
Table 3: Pin Descriptions
Number
4, 5, 8, 9, 13, 16
Function
N/C
Description
No connection necessary, may be connected
to DC/RF ground
Must be connected to DC/RF ground
AC coupled and matched to 50W
Optional 1st and 2nd gate bias lines, required > 100pF
low-freq bypass capacitor if used
1st and 2nd drain bias lines, requires>100pF low-freq
bypass capacitor and clean power supply
1, 3, 10, 12, + paddle
2, 11
6, 7
GND
RF IN, OUT
VG1, VG2
14, 15
VD1, VD2
SMD-00106 Rev C
Subject to Change Without Notice
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UA5M15MP
QB Package Outline
Package Notes:
• Conforms to JEDEC MO-220, revision 1
• Pin 1 ID indicated by dot on top of package
• All units millimeters, not to scale
• Pkg is 100% Pb free (lead free)
• Leadframe base is 0.2mm Cu 194 FH with
Ag-ring finish
• Solder plate is 100% Sn
• All ground leads and center paddle must
be connected to RF ground
Lead Free (Pb-free):
The UA5M15MP QFN package contains no lead (Pb) and eliminates the need for costly
re-qualification efforts, which are necessary to conform to the European mandated “Restricted
use of Hazardous Substances” (RoHS) compliance.
Thermal Heat Sinking:
To avoid damage and for optimum performance, you must observe the maximum channel
temperature and ensure adequate heat sinking. PCB ground planes are not sufficient, the backside
of the QFN must be soldered to the PCB, and PCB filled or plated vias must be used to conduct
heat away from this contact.
ESD Handling and Bonding:
This package is ESD sensitive; preventive measures should be taken during handling and solder
attach. Solder paste and flux screen printing is recommended.
SMD-00106 Rev C
Subject to Change Without Notice
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