NB3M8T3910GEVB
NB3M8T3910G Evaluation
Board User's Manual
Introduction
The NB3M8T3910GEVB is a custom evaluation board
developed by ON Semiconductor for the NB3M8T3910G.
This evaluation board was designed to provide a flexible and
convenient platform to quickly evaluate, characterize and
verify the operation of the NB3M8T3910G.
This evaluation board manual contains:
•
Information on the NB3M8T3910G Evaluation Board
•
Assembly Instructions
•
Test and Measurement Setup Procedures
•
Bill of Materials
Top View
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EVAL BOARD USER’S MANUAL
This manual should be used in conjunction with the device
datasheet
NB3M8T3910/D
which contains full technical
details on the device specifications and operation.
Bottom View
Figure 1. NB3M8T3910GEVB Top and Bottom View
READ FIRST − INTRODUCTION
The NB3M8T3910G has two banks of 5 differential
outputs. Each output bank can be independently selected as
LVPECL, LVDS or HCSL outputs by the SMODEAx/Bx
select pins.
This evaluation board, NB3M8T3910GEVB, has been
configured to evaluate each output type.
Of the ten possible differential outputs, three are dedicated
as LVPECL, three are dedicated as LVDS and four are
dedicated as HCSL (labeled on board).
©
Semiconductor Components Industries, LLC, 2014
The Single-Ended LVCMOS Output, REFOUT, is
controlled by the Synchronous OE_SE pin. For Clock
frequencies above 250 MHz, the REFOUT line should be
disabled.
Each dedicated output pair on the board is configured per
Table 1 below:
1
September, 2014 − Rev. 0
Publication Order Number:
EVBUM2238/D
NB3M8T3910GEVB
Table 1. OUTPUT DEDICATION OF THE NB3M8T3910GEVB
Output Pin Name
QA0/QA0b
QA1/QA1b
QA2/QA2b
Output Type
(Dedicated)
LVPECL
LVPECL
LVDS
SMODEA [1:0]
00
00
01
SMODEB [1:0]
xx
xx
xx
Output Measurement Method
Use 50-W Scope Head; there is no load on the board
Use 50-W Scope Head; there is no load on the board
Measure with Single or Differential Hi-Z Probes; Outputs
have 100-W termination resistor across at SMA
connectors
Use 50-W Scope Head; there is no 50-W to GND on the
board; or install 50-W SMA terminators and use a Hi-Z
probe
Use 50-W Scope Head; there is no 50-W to GND on the
board; or install 50-W SMA terminators and use a Hi-Z
probe
Measure with Single or Differential Hi-Z Probes; these
LVPECL outputs have a Thevenin termination resistor
network.
Measure with Single or Differential Hi-Z Probes; Outputs
have 100-W termination resistor across at SMA
connectors
Measure with Single or Differential Hi-Z Probes; Outputs
have 100-W termination resistor across at SMA
connectors
Measure with Single or Differential Hi-Z Probes; there is
50-W to GND on the board
Use 50-W Scope Head; there is no 50-W to GND on the
board; or install 50-W SMA terminators and use a Hi-Z
probe
QA3/QA3b
HCSL
10
xx
QA4/QA4b
HCSL
10
xx
QB0/QB0b
LVPECL
xx
00
QB1/QB1b
LVDS
xx
01
QB2/QB2b
LVDS
xx
01
QB3/QB3b
QB4/QB4b
HCSL
HCSL
xx
xx
10
10
NOTE: x = don’t care
LVDS OUTPUT CONFIGURATION
Two 0-W Resistors
100-W Resistor
Figure 2. LVDS Output Configuration
LVDS outputs are typically terminated with 100-Ω across
the Q & Qb output pair.
On QA2/QA2b, QB1/QB1b, QB2/QB2b, there are
on-board 100-ohm output termination resistors across the
LVDS outputs. Two 0-Ω resistors connect the metal traces
and a 100-Ω resistor connects between the traces.
Use a single-ended or differential high-impedance probe
across the 100-Ω resistor.
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NB3M8T3910GEVB
HCSL OUTPUT CONFIGURATION
R
series
= 33-W for HCSL Outputs
CL = 2 pF Capacitor
to GND for HCSL
Outputs
Figure 3. HCSL Output Configuration
HCSL outputs are typically loaded and terminated with
a R
series
= 33-W and 50-W to ground. This can be easily
accomplished by connecting the HCSL outputs to the 50-W
internal impedance in the oscilloscope.
On QA3/QA3b, QA4/QA4b, QB3/QB3b, QB4/QB4b,
there are on-board R
series
= 33-W series termination resistors
installed for each HCSL output. Also, there is a CL = 2 pF
installed to GND.
For QA3/QA3b, QA4/QA4b, QB4/QB4b use 50-W to
GND of oscilloscope sampling head to satisfy the HCSL
output loading. QB3/QB3b has a 50-W output load, thus use
a Hi-Z probe for measurements.
LVPECL OUTPUT CONFIGURATION
R
Thevenin
= 130-W to VCC (H) and
80-W to GND (L) for LVPECL Outputs
Figure 4. LVPECL Output Configuration
On QA0/QA0b or QA1/QA1b, there is no on-board
LVPECL output loading or termination.
Use the 50-W to GND of the oscilloscope sampling head
to satisfy the LVPECL output loading and termination. This
single supply scheme will simplify the LVPECL output
testing versus a split power supply.
However, this method
will actually draw more output current with a single power
supply versus a dual/split power supply.
Nevertheless, this
extra output current will be within the Maximum Ratings
limit.
Figure 5. LVPECL Output Configuration,
Thevenin Termination Resistors
On QB0/QB0b, there is an on-board Thevenin output
loading and termination resistor network; 130-W from
LVPECL output to VDDO and 80-W from output to GND.
This arrangement will satisfy the LVPECL DC output
loading and AC termination.
Use single-ended or differential high-impedance probes.
See
AND8020/D,
section 3, for more information.
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NB3M8T3910GEVB
“Split” or Dual Power Supply Connections
Dual Power Supply
QUICK START LAB SET-UP USER’S GUIDE
Power-Up, Input and Output Connections
+2.0 V
+
VCC
−
+
+1.3 V
−
SMAGND DUTGND
+3.3 V
Figure 6. LVPECL – “Split” or Dual Power Supply
Configuration
Most ECL outputs are open emitter and need to be DC
loaded and AC terminated to VCC – 2.0 V via a 50
W
resistor. For standard ECL lab setup and test, a split (dual)
power supply is recommended enabling the 50-W internal
impedance in the oscilloscope, or other measuring
instrument, to be used as an ECL output load/termination.
By offsetting VCC = +2.0 V, SMAGND = VCC – 2.0 V =
0 V, SMAGND is the system ground, 0 V, and DUTGND is
–1.3 V or −0.5 V.
More information on ECL termination is provided in
AND8020/D.
Power Supply Connector
VDD/VDDOx
SMAGND
DUTGND
“Spilt” Power Supply
VCC = +2.0 V
VTT = 0 V
DUTGND = −1.3 V for 3.3 V
p/s or −0.5 V for 2.5 V p/s
1. Connect the VDD and VDDOx banana jacks with
power supply cables to +3.3 V, and DUTGND
and SMAGND to 0 V.
2. Select Crystal input and monitor 25 MHz on each
Qn output.
3. Connect a signal generator to the SMA connectors
for CLK0/CLK0b or CLK1/CLK1b inputs.
50-ohm termination resistors are installed for
a signal generator on the board. Set appropriate
input signal levels and frequency.
4. Observe the Qn outputs with a high-Z probe
oscilloscope.
Table 2. POWER SUPPLY CONNECTIONS
Device Pin
Power Supply Connector
VDD
VDDOx
SMAGND
DUTGND
Power Supply
+3.3 V
+3.3 V
0V
0V
Single Power Supply Connections
Single Power Supply
+3.3 V
+
0V
−
LVCMOS OUTPUT CONFIGURATION
On REFOUT use a Hi−Z probe or the following set up to
use a 50
W
to GND sampling head Oscilloscope.
“Split” or Dual Power Supply Connections
Dual Power Supply
VDD/VDDOx
SMAGND/DUTGND
+3.3 V
Figure 8. Single Power Supply Configuration
+1.65 V
+
−
VCC
+1.65 V
+
−
SMAGND DUTGND
+3.3 V
Figure 7. LVCMOS – “Split” or Dual Power Supply
Configuration
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NB3M8T3910GEVB
VDDOC
VDD
VDDOB
Signal Generator
Oscilloscope
OUT
OUTb
Q
Qb
Trigger In
Trigger Out
SMAGND
VDDOA
DUTGND
Figure 9. Typical Lab Test Set-Up
Board Layout
The custom QFN−48 Evaluation Board provides a high
bandwidth, 50-W controlled impedance environment and is
implemented in four layers. The first layer or primary
“high-speed” trace layer is FR4 material, and is designed to
have equal electrical length on all signal traces from the
device under test (DUT) pins to the SMA connectors. The
second layer is the 0.5 oz copper ground plane and is
dedicated for the SMA connector ground plane. FR4
dielectric material is placed between the second and third
layers and between third and fourth layers. The third layer
is also 0.5 oz copper plane. A portion of this layer is
designated for the device VDD and DUTGND power
planes. The fourth layer is the VDDOx layer.
Layer Stack
L1 (top) High Speed Signal (FR4)
L2 SMAGND − SMA Ground (FR4)
L3 VDD and DUTGND (FR4)
L4 (bottom) VDDOx and DUTGND (FR4)
Figure 10. QFN−48 Evaluation Board Layout, 4-Layer Stack
Table 2 and Figure 8 describes the board configuration for
the power supplies, Figure 3 shows typical input and output
connections.
VDD
is the positive power supply.
VDDOA, VDDOB, VDDOC
are the positive power
supplies for the outputs.
DUTGND (Device Under Test Ground)
is the negative
power supply for the device. Banana jack is labeled
DUTGND.
Exposed Pad (EP).
The exposed pad footprint on the board
is mechanically connected (soldered) to the exposed pad of
the QFN−48 package, and is electrically connected to
DUTGND power supply.
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