1.6mm, glass epoxy 4-layer board, with backside mounting.
Caution 1) Absolute maximum ratings represent the value which cannot be exceeded for any length of time.
Caution 2) Even when the device is used within the range of absolute maximum ratings, as a result of continuous usage under high temperature, high current,
high voltage, or drastic temperature change, the reliability of the IC may be degraded. Please contact us for the further details.
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality should not be assumed,
damage may occur and reliability may be affected.
Recommended Operating Range
at Ta = 25C
Parameter
Range of power supply voltage
Logic input voltage
Range of VREF input voltage
Symbol
VM
VIN
VREF
VM , VM1 , VM2
GMG1 , GMG2 , GAD , FR , STEP , ST ,
RST , MD1 , MD2 , OE , GST1 , GST2
0 to 3
V
Conditions
Ratings
9 to 32
0 to 5.5
Unit
V
V
Functional operation above the stresses listed in the Recommended Operating Ranges is not implied. Extended exposure to stresses beyond the Recommended
Operating Ranges limits may affect device reliability.
Electrical Characteristics
at Ta = 25°C, VM = 24V, VREF = 1.5V
Parameter
Consumption current during
standby
Consumption current
VREG5 output voltage
Thermal shutdown temperature
Thermal hysteresis width
Motor driver
Output on resistor
Ronu
Rond
Output leak current
Forward diode voltage
Logic pin input current
IOleak
VD
IINL
IINH
ADIN pin input voltage
Logic input
voltage
High
Low
Vadin
VINH
VINL
IO = 2.5A, Source-side Ron
IO = 2.5A, Sink-side Ron
VM = 32V
ID = -2.5A
VIN = 0.8V
VIN = 5V
GMG1, GMG2, GAD, FR,
STEP, ST, RST, MD1,
MD2, OE, GST1, GST2
0
2.0
0
12
5.5
0.8
V
V
V
4
30
1.2
8
50
0.3
0.25
0.4
0.33
50
1.4
12
70
A
V
A
A
IM
VREG5
TSD
TSD
ST = ”H”, OE = ”L”, STEP = ”L”, non-load
I(VM)+I(VM1)+I(VM2)
IO = -1mA
Design certification
Design certification
4.5
150
5
180
40
5.5
210
V
C
C
4.5
6.5
mA
Symbol
IMstn
Conditions
ST = ”L” , I(VM)+I(VM1)+I(VM2)
Ratings
min
typ
110
max
400
Unit
A
Ra2 = 100k: refer to 15-4)
GMG1 , GMG2 , GAD , FR , STEP , ST ,
RST , MD1 , MD2 , OE , GST1 , GST2
Continued on next page.
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2
LV8702V
Continued from preceding page.
Parameter
Current
selection
reference
voltage level
half step
quarter step
Symbol
Vtdac0_W
Vtdac1_W
Vtdac2_W
Vtdac3_W
Vtdac0_H
Vtdac2_H
half step
(full-torque)
full step
Chopping frequency
CHOP pin charge/discharge
current
Chopping oscillator circuit
threshold voltage
VREF pin input current
DST1, DST2, MONI,
SST pin saturation voltage
Charge pump
VG output voltage
Rise time
Oscillator frequency
VG
tONG
Fosc
VG = 0.1F , Between CP1-CP2 0.1uF
ST=”H”
→
VG=VM+4V
90
125
160
kHz
28
28.7
29.8
0.5
V
mS
Vtup
Vtdown
Iref
VREF = 1.5V
Idst1 = Idst2 = Imoni = Isst = 1mA
0.8
0.4
0.5
400
1
0.5
1.2
0.6
V
V
A
mV
Vtdac0_HF
Vtdac2’_HF
Vtdac2’_F
Fchop
Ichop
Conditions
Step0 (initial status, 1ch comparator level)
Step1 (initial + 1)
Step2 (initial + 2)
Step3 (initial + 3)
Step0 (initial status, 1ch comparator level)
Step2 (initial + 1)
Step0 (initial status, 1ch comparator level)
Step2’ (initial + 1)
Step2’ (initial status, 1ch comparator level)
Cchop = 200pF
Ratings
min
290
264
199
106
290
199
290
290
290
35
7
typ
300
276
210
114
300
210
300
300
300
50
10
max
310
288
221
122
310
221
310
310
310
65
13
Unit
mV
mV
mV
mV
mV
mV
mV
mV
mV
kHz
A
Product parametric performance is indicated in the Electrical Characteristics for the listed test conditions, unless otherwise noted. Product performance may not be
indicated by the Electrical Characteristics if operated under different conditions.
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3
LV8702V
Package Dimensions
unit : mm
SSOP44J (275mil) Exposed Pad
CASE 940AG
ISSUE A
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4
LV8702V
SOLDERING FOOTPRINT*
(Unit: mm)
(7.8)
(3.6)
1.00
0.32
XXXXXXXXXX
YMDDD
0.65
NOTES:
1. The measurements are for reference only, and unable to guarantee.
2. Please take appropriate action to design the actual Exposed Die Pad and Fin portion.
3. After setting, verification on the product must be done.
(Although there are no recommended design for Exposed Die Pad and Fin portion Metal mask and shape
for Through−Hole pitch (Pitch & Via etc), checking the soldered joint condition and reliability verification of
soldered joint will be needed. Void gradient insufficient thickness of soldered joint or bond degradation
could lead IC destruction because thermal conduction to substrate becomes poor.)
*For additional information on our Pb−Free strategy and soldering details, please download the ON Semiconductor
Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
GENERIC
MARKING DIAGRAM*
XXXXX = Specific Device Code
Y = Year
M = Month
DDD = Additional Traceability Data
6.0
Pd max -- Ta
Four-layer circuit board *1
5.5
Allowable power dissipation, Pd max -- W
5.0
4.0
Four-layer circuit board *2
3.8
3.0
7.00
2.9
2.0
0
20
40
60
80
2.0
1.0
*1 With components mounted on the exposed die-pad board
*2 With no components mounted on the exposed die-pad board
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