HB0093
Handbook
Core1553BRT v4.2
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50200093.6.0 3/17
Core1553BRT v4.2 Handbook
Table of Contents
Introduction.............................................................................................................................................................5
Core Overview.......................................................................................................................................................................... 5
Verification and Compliance................................................................................................................................................... 7
Fail-Safe State Machines
........................................................................................................................................................
7
Core Version
.............................................................................................................................................................................
7
Supported Families
..................................................................................................................................................................
7
Device Requirements
..............................................................................................................................................................
8
1 MIL-STD-1553B Bus Overview
...........................................................................................................................
9
Message Types
........................................................................................................................................................................
9
Word Formats
.........................................................................................................................................................................
10
2 Tool Flows
...........................................................................................................................................................
11
SmartDesign
...........................................................................................................................................................................
11
Simulation Flows
....................................................................................................................................................................
12
Precompiled Libraries
...........................................................................................................................................................
12
3 Interface Descriptions
........................................................................................................................................
13
Parameters on Core1553BRT
.............................................................................................................................................
13
I/O Signal Descriptions
..........................................................................................................................................................
15
4 Interface Timing
..................................................................................................................................................
20
Specifications
.........................................................................................................................................................................
20
Transceiver Loopback Delays
..............................................................................................................................................
25
Clock Requirements
..............................................................................................................................................................
25
5 Operation
.............................................................................................................................................................
26
Standard Memory Address Map
..........................................................................................................................................
26
1553 Memory Usage
.............................................................................................................................................................
26
Memory Address Mapping
....................................................................................................................................................
28
Interrupt Vector Extension
....................................................................................................................................................
29
Status Word Settings
.............................................................................................................................................................
29
Command Word Storage
......................................................................................................................................................
29
Transfer Status Words
..........................................................................................................................................................
30
Backend Access Times
.........................................................................................................................................................
30
Data Transfers – Receive
.....................................................................................................................................................
31
Data Transfers – Transmit
....................................................................................................................................................
31
RT-to-RT Transfer Support
..................................................................................................................................................
31
Mode Codes
...........................................................................................................................................................................
31
Loopback Tests
......................................................................................................................................................................
32
Error Detection
.......................................................................................................................................................................
33
Built-In Test Support
..............................................................................................................................................................
34
Command Legalization Interface
.........................................................................................................................................
35
6 Testbench Operation and Modification
...........................................................................................................
36
Revision 6
3
Table of Contents
Verification Testbench
...........................................................................................................................................................
36
VHDL Testbench
....................................................................................................................................................................
41
Verilog Testbench
..................................................................................................................................................................
45
7 Implementation Hints
.........................................................................................................................................
50
External Command Word Legality Example
......................................................................................................................
51
Modifying the Backend Address Map
.................................................................................................................................
54
Modifying the Backend Interrupt Vector.............................................................................................................................. 56
Connecting the Backend to Internal FPGA Memory
.........................................................................................................
58
Buffer Management
...............................................................................................................................................................
58
Bus Transceivers
...................................................................................................................................................................
59
Typical RT Systems
...............................................................................................................................................................
60
8 VHDL Testbench Procedure and Function Calls
...........................................................................................
62
9 Ordering Information
..........................................................................................................................................
64
Ordering Codes
......................................................................................................................................................................
64
List of Changes
...................................................................................................................................................
65
4
Revision 6
Introduction
Core Overview
Core1553BRT provides a complete, dual-redundant MIL-STD-1553B remote terminal (RT), apart from
the transceivers required to interface to the bus. A typical system implementation using Core1553BRT is
shown in
Figure a-1
and
Figure a-2 on page 6.
ADC
Backend
Interface
Address
Mapper
Memory
BUSAINEN
BUSAINP
BUSAINN
BUSAOUTIN
BUSAOUTP
BUSAOUTN
RCVSTBA
RXDAINP
RXDAINN
TXINHA
TXDAINP
TXDAINN
Transceiver
Command
Legality
Checker
Command
Legality
Interface
BUSBINEN
BUSBINP
BUSBINN
BUSBOUTIN
BUSBOUTP
BUSBOUTN
RCVSTBB
RXDBINP
RXDBINN
TXINHB
TXDBINP
TXDBINN
Core1553BRT
Microsemi FPGA
Figure a-1 •
Typical Core1553BRT System
At a high level, Core1553BRT simply provides a set of memory-mapped subaddresses that “receive data
written to” or “transmit data read from.” The core can be configured to connect directly to synchronous or
asynchronous memory devices. Alternatively, the core can directly connect to backend devices,
removing the need for memory buffers. If memory is used, the core requires 2,048 words of memory,
which can be shared with the local CPU.
The core supports all 1553B mode codes and allows the user to designate as illegal any mode code or
any particular subaddress for both transmit and receive operations. The command legalization can be
done within the core or in an external command legality block via the command legalization interface.
Revision 6
5
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