Core1553BBC MIL-STD-1553B Bus Controller
Product Summary
Intended Use
•
•
1553B Bus Controller (BC)
DMA Backend Interface to External Memory
– Synthesis Scripts
Actel-Developed Testbenches, VHDL and Verilog
•
Synthesis and Simulation Support
•
•
Synthesis: Synplicity
®
, Synopsys
®
(Design Compiler
®
/
FPGA Compiler
TM
/FPGA Express
TM
), Exemplar
TM
Simulation: Vital-Compliant VHDL Simulators and
OVI-Compliant Verilog Simulators
Key Features
•
•
Supports MIL-STD-1553B
Interfaces to External RAM
– Supports up to 128kbytes of Memory
– Synchronous
or
Asynchronous
Backend
Interface
– Backend Interface Identical to Core1553BRT
Selectable Clock Rate of 12, 16, 20, or 24 MHz
Provides Direct CPU Access to Memory
Interfaces to Standard 1553B Transceivers
Fully Automated Message Scheduling
– Frame Support
– Conditional Branching and Sub-routines
– Variable Inter-message Gaps and RT Response
Times
– Real Time Clock for Message Scheduling
– Asynchronous Message Support
Verification and Compliance
•
•
•
Actel-Developed Simulation Testbench
Core Implemented on the 1553B BC Development
System
Third-Party 1553B Compliance Testing of the
1553B Encoder and Decoder Blocks Implemented
in an A54SXA32-STD Device
•
•
•
•
Development System (Optional)
•
•
•
Complete 1553B BC Implementation in an SX-A
Device
Includes a PCI Interface for Host CPU Connection
Includes Transceivers
Components
and
Bus
Termination
Supported Families
•
•
•
•
•
•
•
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX
SX-A
RTSX-S
Contents
General Description ................................................... 2
Core1553BBC Device Requirements .......................... 4
Core1553BBC Verification and Compliance .............. 4
MIL-STD-1553B Bus Overview .................................... 4
I/O Signal Descriptions ............................................. 6
Bus Transceivers ........................................................ 20
Development System ............................................... 20
Typical BC System ..................................................... 22
Specifications ............................................................ 24
Ordering Information .............................................. 28
List of Changes ......................................................... 29
Datasheet Categories ............................................... 29
Core Deliverables
•
Netlist Version
Compiled RTL Simulation Model, Compliant
with the Actel Libero™ Integrated Design
Environment (IDE)
– Compatible with the Actel Designer Place-and-
Route Tool
RTL Version
– VHDL or Verilog Core Source Code
–
•
December 2005
© 2005 Actel Corporation
v 4 .0
1
Core1553BBC MIL-STD-1553B Bus Controller
General Description
The Core1553BBC provides a complete, MIL-STD-1553B
Bus Controller (BC). A typical system implementation
using the Core1553BBC is shown in
Figure 1.
Core1553BBC reads message descriptor blocks from the
memory and generates messages that are transmitted on
the 1553B bus. Data words are read from the memory
and transmitted on the 1553B bus. Data received is
written to the memory. The core can be configured
directly to connect to synchronous or asynchronous
memory devices.
The core consists of five main blocks: the 1553B encoder,
the 1553B decoder, a protocol controller block, a CPU
interface, and a backend interface (Figure
2).
Backend
Interface
Memory
BUSAINEN
BUSAINP
BUSAINN
BUSAOUTINH
BUSAOUTP
BUSAOUTN
RCVSTBA
RXDAIN
RXDAIN
TXINHA
TXDAIN
TXDAIN
Transceiver
(Not Included)
RCVSTBA
RXDBIN
RXDBIN
TXINHA
TXDBIN
TXDBIN
Glue
Logic
CPU
CPU
Interface
Encoder
Decoder
BUSBINEN
BUSBINP
BUSBIN
BUSAOUTINH
BUSBOUTP
BUSBOUTN
Core1553BBC
Actel FPGA
Figure 1 •
Typical Core1553BBC System
BusA
Protocol
Controller
BusB
Backend
Interface
CPU
Interface
and
Registers
Core1553BBC
Memory
64K*16
Figure 2 •
Core1553BBC BC Block Diagram
2
v4.0
Core1553BBC MIL-STD-1553B Bus Controller
A single 1553B encoder takes each word to be
transmitted and serializes it using Manchester encoding.
The encoder includes independent logic to prevent the
BC from transmitting for greater than the allowed
period and to provide loopback fail logic. The loopback
logic monitors the received data and verifies that the
core has correctly received every word that is
transmitted. The encoder output is gated with the bus
enable signals to select which buses the RT should be
transmitting.
Since the BC knows which bus is in use at any time, only a
single decoder is required. The decoder takes the serial
Manchester received data from the bus and extracts the
received data words. The decoder requires a 12, 16, 20,
or 24 MHz clock to extract the data and the clock from
the serial stream.
The decoder contains a digital phased lock loop (PLL)
that generates a recovery clock used to sample the
incoming serial data. The data is then deserialized and
the 16-bit word decoded. The decoder detects whether a
command, status or data word has been received and
checks that no Manchester encoding or parity errors
occurred in the word.
The protocol controller block handles all the message
sequencing and error recovery. This is a complex state
machine that reads the 1553B message frames from the
memory and transmits them on the 1553B bus.
The CPU interface allows the system CPU to access the
control registers within the BC. It also allows the CPU to
directly access the memory connected to the backend
interface. These features can simplify system design.
The backend interface for the Core1553BBC allows a
simple connection to a memory device. The backend
interface can be configured to connect to either
synchronous or asynchronous memory devices. This
allows the core to be connected to synchronous logic or
memory within the FPGA or to external asynchronous
memory blocks. The interface supports a standard bus
request and grant protocol and provides a WAIT input,
allowing the core to interface to slow memory devices.
This allows the core to share system memory rather than
have its own dedicated memory block.
Core1553BBC Operation
A bus controller is responsible for sending data bus
commands, participating in data transfers, receiving
status responses, and monitoring the bus system. The
system CPU will create message lists in the BC memory, as
illustrated in
Figure 3.
When started, the BC works its way through the message
lists. The Core1553B transmits the specified 1553B
command and data words, and receives the 1553B status
word and associated data words and writes them to the
BC memory. During this process, the BC monitors all
possible 1553B error conditions. If an RT does not
respond correctly, the BC will retry the message on both
the original bus and the alternate bus.
Instruction
List
Message
Block
Data
Block
INSTRUCTION
PARAMETER
INSTRUCTION
PARAMETER
INSTRUCTION
PARAMETER
MSGCMD
CW (RTRT RX)
CW (RTRT TX)
DATAPTR
SW (RTRT TX)
SW (RTRT RX)
TSW
32
Data Words
Figure 3 •
Message Lists
v4.0
3
Core1553BBC MIL-STD-1553B Bus Controller
Core1553BBC Device Requirements
The Core1553BBC can be implemented in several Actel FPGA devices.
Table 1
shows typical utilization figures for the
Core1553BBC implemented in these devices.
Table 1 •
Device Utilization
Cells or Tiles
Family
Fusion
ProASIC3/E
ProASIC
PLUS
Axcelerator
RTAX-S
SX-A
RTSX-S
Combinatorial
1773
1773
2250
1072
1072
1115
1098
Sequential
558
558
560
584
584
589
598
Total
2331
2331
2810
1656
1656
1704
1696
Device
AFS600
A3PE600
APA150-STD
AX500-STD
RTAX250-STD
A54SX32A-STD
RT54SX32S-STD
Utilization
17%
17%
46%
20%
9%
56%
57%
The Core1553BBC clock rate can be programmed to 12,
16, 20, or 24 MHz. All Actel device families listed in
Table 1
easily meet this performance requirement.
When implemented in ProASIC
PLUS
or Axcelerator
devices, the Core1553BBC can connect directly to the
internal FPGA memory blocks, eliminating the need for
external memories.
MIL-STD-1553B Bus Overview
The MIL-STD-1553B bus is a differential serial bus used in
military and space equipment. It is comprised of multiple
redundant bus connections and communicates at 1MB
per second.
The bus has a single active bus controller (BC) and up to
31 remote terminals (RTs). The BC manages all data
transfers on the bus using the command and status
protocol. The bus controller initiates every transfer by
sending a command word and data if required. The
selected RT will respond with a status word and data if
required.
The 1553B command word contains a five-bit RT address,
a transmit or receive bit, a five-bit sub-address and a five-
bit word count. This allows for 32 RTs on the bus.
However, since RT address 31 is used to indicate a
broadcast transfer, only 31 RTs may be connected. Each
RT has 30 sub-addresses reserved for data transfers. The
other two sub-addresses (0 and 31) are reserved for
mode codes. Data transfers contain up to (32) 16-bit data
words. Mode code command words are used for bus
control functions such as synchronization.
Core1553BBC Verification and
Compliance
Core1553BBC is based upon the Actel Core1553BRT,
which has been fully verified against the RT validation
Test Plan (MIL-HDBK-1553A, Appendix A). This ensures
that the 1553B encoders and decoders are fully
compliant to the 1553B specification. The actual bus
controller function has been extensively verified in both
simulation and hardware. Core1553BBC has been
implemented on an A54SX32A-STD part connected to
external transceivers and memory.
4
v4.0
Core1553BBC MIL-STD-1553B Bus Controller
Message Types
The 1553B bus supports ten message transfer types, allowing basic point-to-point and broadcast BC to RT data
transfers, mode code messages, and direct RT-to-RT messages.
Figure 4
shows the message formats.
BC-to-RT Transfer
BC
Transmit
Command
Data
0
Data
...
Data
n
Response
Time
RT
Status
Word
Message
Gap
BC
Next
Command
RT-to-BC Transfer
BC
Receive
Command
Response
Time
RT
Status
Word
Data
0
Data
...
Data
n
Message
Gap
BC
Next
Command
RT-to-RT Transfer
BC
Receive
Transmit
Command Command
BC-to-all-RTs Broadcast
BC
Transmit
Command
Data
0
Data
...
Data
n
Message
Gap
BC
Next
Command
Response
Time
RT1
Status
Word
Data
0
Data
...
Data
n
Response
Time
RT2
Status
Word
Message
Gap
BC
Next
Command
RT-to-all RTs Broadcast
BC
Receive
Transmit
Command Command
Response
Time
RT
Status
Word
Data
0
Data
...
Data
n
Message
Gap
BC
Next
Command
Mode Command, No Data
BC
Mode
Command
Response
Time
RT
Status
Word
Message
Gap
BC
Next
Command
Mode Command, RT Transmit Data
BC
Mode
Command
Response
Time
RT
Status
Word
Mode
Data
Message
Gap
BC
Next
Command
Mode Command, RT Receive Data
BC
Mode
Command
Mode
Data
Response
Time
RT
Status
Word
Message
Gap
BC
Next
Command
Broadcast Mode Command, No Data
BC
Mode
Command
Message
Gap
BC
Next
Command
Broadcast Mode Command with Data
BC
Mode
Command
Mode
Data
Message
Gap
BC
Next
Command
Figure 4 •
1553B Message Formats
v4.0
5
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