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89KTPES22H16G2: 产品描述Interface Development Tools EVAL KIT FOR 89H22H16G2; 产品类别开发板/开发套件/开发工具; 文件大小347KB，共57页; 制造商IDT(艾迪悌); 官网地址http://www.idt.com/

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89KTPES22H16G2概述

Interface Development Tools EVAL KIT FOR 89H22H16G2

89KTPES22H16G2规格参数

参数名称	属性值
产品种类 Product Category	Interface Development Tools
制造商 Manufacturer	IDT(艾迪悌)
RoHS	No
系列 Packaging	Bulk
工厂包装数量 Factory Pack Quantity	1

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22-Lane 16-Port PCIe® Gen2

System Interconnect Switch

89HPES22H16G2

Data Sheet

Device Overview

The 89HPES22H16G2 is a member of the IDT PRECISE™ family of

PCI Express® switching solutions. The PES22H16G2 is a 22-lane, 16-

port system interconnect switch optimized for PCI Express Gen2 packet

switching in high-performance applications, supporting multiple simulta-

neous peer-to-peer traffic flows. It provides connectivity and switching

functions between a PCI Express upstream port and up to fifteen down-

stream ports and supports switching between downstream ports.



• Drive strength

Switch Partitioning

Features



High Performance Non-Blocking Switch Architecture

–

Sixteen maximum switch ports

• Two x4 ports

• Fourteen x1 ports

–

Integrated SerDes supports 5.0 GT/s Gen2 and 2.5 GT/s

Gen1 operation

–

Delivers 22 GBps (176 Gbps) of aggregate switching capacity

–

Supports up to 128 Bytes to 2 KB maximum payload size

–

Low latency cut-through architecture

–

Supports one virtual channel and eight traffic classes



Standards and Compatibility

–

PCI Express Base Specification 2.0 compliant

–

Implements the following optional PCI Express features

• Advanced Error Reporting (AER) on all ports

• End-to-End CRC (ECRC)

• Access Control Services (ACS)

• Power Budgeting Enhanced Capability

• Device Serial Number Enhanced Capability

• Sub-System ID and Sub-System Vendor ID Capability

• Internal Error Reporting ECN

• Multicast ECN

• VGA and ISA enable

• L0s and L1 ASPM

• ARI ECN



Port Configurability

–

x4, x2, and x1 ports

• Ability to merge adjacent x4 ports to create a x8 port

–

Automatic per port link width negotiation (x4

→

x1)

–

Crosslink support

–

Automatic lane reversal

–

Autonomous and software managed link width and speed

control

–

Per lane SerDes configuration

• De-emphasis

• Receive equalization

–

IDT proprietary feature that creates logically independent

switches in the device

–

Supports up to 16 fully independent switch partitions

–

Configurable downstream port device numbering

–

Supports dynamic reconfiguration of switch partitions

• Dynamic port reconfiguration — downstream, upstream

• Dynamic migration of ports between partitions

• Movable upstream port within and between switch partitions



Initialization / Configuration

–

Supports Root (BIOS, OS, or driver), Serial EEPROM, or

SMBus switch initialization

–

Common switch configurations are supported with pin strap-

ping (no external components)

–

Supports in-system Serial EEPROM initialization/program-

ming



Quality of Service (QoS)

–

Port arbitration

• Round robin

–

Request metering

• IDT proprietary feature that balances bandwidth among

switch ports for maximum system throughput

–

High performance switch core architecture

• Combined Input Output Queued (CIOQ) switch architecture

with large buffers



Multicast

–

Compliant to the PCI-SIG multicast ECN

–

Supports arbitrary multicasting of Posted transactions

–

Supports 64 multicast groups

–

Multicast overlay mechanism support

–

ECRC regeneration support



Clocking

–

Supports 100 MHz and 125 MHz reference clock frequencies

–

Flexible port clocking modes

• Common clock

• Non-common clock

• Local port clock with SSC and port reference clock input



Hot-Plug and Hot Swap

–

Hot-plug controller on all ports

• Hot-plug supported on all downstream switch ports

–

All ports support hot-plug using low-cost external I

C I/O

expanders

–

Configurable presence detect supports card and cable appli-

cations

IDT and the IDT logo are registered trademarks of Integrated Device Technology, Inc.

1 of 57



2011 Integrated Device Technology, Inc.

November 28, 2011

IDT 89HPES22H16G2 Data Sheet

SMBus Interface

The PES22H16G2 contains two SMBus interfaces. The slave interface provides full access to the configuration registers in the PES22H16G2,

allowing every configuration register in the device to be read or written by an external agent. The master interface allows the default configuration

register values of the PES22H16G2 to be overridden following a reset with values programmed in an external serial EEPROM. The master interface is

also used by an external Hot-Plug I/O expander.

Each of the two SMBus interfaces contain an SMBus clock pin and an SMBus data pin. In addition, the slave SMBus has SSMBADDR1 and

SSMBADDR2 pins. As shown in Figure 3, the master and slave SMBuses may only be used in a split configuration.

Switch

Processor

SMBus

Master

...

Other

SMBus

Devices

SSMBCLK

SSMBDAT

MSMBCLK

MSMBDAT

Serial

EEPROM

Hot-Plug

I/O

Expander

Figure 3 Split SMBus Interface Configuration

The switch’s SMBus master interface does not support SMBus arbitration. As a result, the switch’s SMBus master must be the only master in the

SMBus lines that connect to the serial EEPROM and I/O expander slaves. In the split configuration, the master and slave SMBuses operate as two

independent buses; thus, multi-master arbitration is not required.

Hot-Plug Interface

The PES22H16G2 supports PCI Express Hot-Plug on each downstream port (ports 1 through 15). To reduce the number of pins required on the

device, the PES22H16G2 utilizes an external I/O expander, such as that used on PC motherboards, connected to the SMBus master interface.

Following reset and configuration, whenever the state of a Hot-Plug output needs to be modified, the PES22H16G2 generates an SMBus transaction

to the I/O expander with the new value of all of the outputs. Whenever a Hot-Plug input changes, the I/O expander generates an interrupt which is

received on the IOEXPINTN input pin (alternate function of GPIO) of the PES22H16G2. In response to an I/O expander interrupt, the PES22H16G2

generates an SMBus transaction to read the state of all of the Hot-Plug inputs from the I/O expander.

General Purpose Input/Output

The PES22H16G2 provides 54 General Purpose I/O (GPIO) pins that may be individually configured as general purpose inputs, general purpose

outputs, or alternate functions. Some GPIO pins are shared with other on-chip functions. These alternate functions may be enabled via software,

SMBus slave interface, or serial configuration EEPROM.

Pin Description

The following tables list the functions of the pins provided on the PES22H16G2. Some of the functions listed may be multiplexed onto the same

pin. The active polarity of a signal is defined using a suffix. Signals ending with an “N” are defined as being active, or asserted, when at a logic zero

(low) level. All other signals (including clocks, buses, and select lines) will be interpreted as being active, or asserted, when at a logic one (high) level.

Differential signals end with a suffix “N” or “P.” The differential signal ending in “P” is the positive portion of the differential pair and the differential signal

ending in “N” is the negative portion of the differential pair.

4 of 57

November 28, 2011

89KTPES22H16G2

89KTPES22H16G2在线购买

89KTPES22H16G2概述

89KTPES22H16G2规格参数

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