Si321xPPQx-EVB
E
VALUATION
B
OARD
Description
This document describes the operation of the Silicon
Laboratories ProSLIC
®
device evaluation platform. The
devices supported by this document are the Si3210/15/
16 and Si3210M/15M/16M; both Si3201 and discrete
interface topologies are included. Schematics and
layouts are provided for the various ProSLIC products.
The ProSLIC evaluation platform is designed to provide
observation of the ProSLIC’s functionality. The ProSLIC
platform consists of a ProSLIC motherboard, a device-
specific daughter card, and the ProSLIC LINC™
software. The ProSLIC LINC software is a Windows
®
-
based program that can run in Microsoft Windows
environments.
Equipment requirements:
PC running Windows NT, 2000, or XP
25-pin D male-male cable
+5 V, 0.5 A power supply
+3.3 V, 0.5 A power supply (optional)
+12 V, 0.5 A power supply (Si3210, Si3215, Si3216)
Optional equipment:
Balanced audio generator and analyzer
FOR THE
S i 3 2 1 0 / 1 5 / 1 6 P
RO
SLIC
®
8 kHz PCM signal generator and analyzer
(e.g., Audio Precision System 2 and Audio Precision SIA-
2322 and/or Wandel and Goltermann PCM-4)
Features
Silicon Laboratories ProSLIC device
All components necessary for linecard
implementation
Selectable secondary protection
Control I/O through standard Parallel Port
On-board PCLK and FSYNC clock generation for
stand-alone operation
PCM I/O set up for Audio Precision System 2 or
Wandel and Goltermann PCM-4
Full access to PCM highway
Multiple daughter cards may be stacked for multi-
channel evaluation and daisy chain control
ProSLIC power selection (3.3 or 5 V)
Related Documentation
ProSLIC LINC™ User Guide
(e.g., Audio Precision System 2 and/or HP TIMS set and/
or Wandel and Goltermann PCM-4)
Functional Block Diagram
GND +3.3 V +5 V
VIN
Parallel Port
Power In
PCM TX
On-Board
PCM Clock
Generator
ProSLIC Motherboard
Si321x Daughter Card
RJ-11
Port
PC running ProSLIC LINC
software
Rev. 1.2 7/08
PCM RX
Audio
Generator/
Analyzer
Copyright © 2015 by Silicon Laboratories
Si321xPPQx-EVB
Si321xPPQx-EVB
1. Introduction
The ProSLIC Si321x evaluation platform is a modular
system consisting of a generic motherboard and one or
more Si321x device-specific daughter cards. Using the
EVB hardware and ProSLIC LINC™ software, one can
easily configure, control, and monitor Si321x operation.
Up to eight Si321x daughter cards may be stacked
vertically and accessed using uniquely-assigned
timeslots on the common PCM interface and the SPI in
daisy-chain mode.
Motherboard hardware schematics are found in Figures
25, 26, and 27.
All power and signal connections are made to the
motherboard as described in Table 2.
Signal requirements for ProSLIC operation are PCLK,
FS, and Serial IO. The ProSLIC motherboard has a
local oscillator with a programmable logic device to
provide the ProSLIC PCLK FS signals. The DIP switch
(S2) sets the PCLK frequency and controls the FS
enable. See Table 3 for S2 settings. Factory default
setting is for a 2.048 MHz PCLK with F5 enabled. JP3
and JP4 select this internal clock source or an external
PCM clock source. The ProSLIC motherboard has been
designed to directly connect to an Audio Precision SIA-
2322 Serial Interface Adapter through the 15 pin d-
connectors, P2 and P3 (not installed). See Table 5 for
the Audio Precision settings. The ProSLIC evaluation
board has also been designed to interface with a
Wandel and Goltermann PCM-4 through J8, J9, J10,
and J11 (not installed). See Table 6 for PCM-4 settings.
A header, J5 (not installed), allows access to the
ProSLIC’s PCM signals for connection to other PCM
testing devices or an actual telephone system PCM
bus. TIP and RING of the two wire analog interface is
present at the RJ-11 connector, J1.
The ProSLIC evaluation board is voltage-programmable
with specific jumper settings. JP1 selects 3 or 5 V
ProSLIC operation. JP2 selects 3 or 5 V PCM source
level compatibility. These should be placed on the
expected setting. Table 4 shows a summary of JP1–4
settings.
Power is connected to the ProSLIC at J3 and J4, and
supply connections are summarized in Table 1. The 5 V
is always required for the buffers, U2 and U3, to
interface to the parallel port. The ProSLIC can be
powered from 5 V or 3 V with the placement of a jumper
on JP1. The Protection Return connections on J6 are to
be connected to an appropriate ground for TIP/RING
fault testing. This return is tied to signal ground on
board, although it has a dedicated trace for high-current
conditions. Serial control of the ProSLIC is achieved by
toggling select bits of a standard parallel port. The
parallel port connection is available at P1 and J1.
The ProSLIC card can be daisy-chained by simply
stacking the cards. Stack up to eight cards by aligning
JS1–JS6 and pressing together. The ProSLIC LINC
Software allows channel-specific commands by clicking
the
Daisy Chain
button.
1.1. ProSLIC LINC evaluation software
The ProSLIC LINC software is an executable program
that allows control and monitoring of the ProSLIC. It
utilizes the primary LPT port of a standard PC to
communicate to the ProSLIC’s SPI port.
To install the software, insert the Silicon Laboratories
ProSLIC CD into the computer. The setup routine can
be invoked by running the setup.exe program in the root
directory of the CD.
Invoking the ProSLIC LINC is achieved by double
clicking the ProSLIC LINC icon. Refer to the ProSLIC
LINC User Guide for software operation.
1.2. Si321xPPT-EVB ProSLIC Evaluation
Board Description
Si321x EVB daughter cards currently supported by this
hardware solution are listed in Table 1 along with
supporting hardware schematics and layout references
included in this data sheet.
Table 1. Supported Si321x EVB Daughter Cards
EVB Daughter Card Board
Description
Si3210/5/6 QFN with Si3201
integrated line interface
Si3210/5/6 QFN with discrete
line interface
Si3210/5/6M QFN with Si3201
integrated line interface
Schematic Layout
Figures
Figures
1, , 3
7, , 9
4, 5, 6
10, 11, 12
13, 14, 15 16, 17, 18
Si3210/5/6M QFN with discrete 19, 20, 21 22, 23, 24
line interface
2
Rev. 1.2
Si321xPPQx-EVB
Table 2. Motherboard Power Connections
J2, J3, J4
Si321x
VBRING
VBHI
VBLO
GND
GND
GND
+3 V
+5 V
+VIN
+3.3 V
2
+5 V
+9 to 12 V
3
+3.3 V
2
+5 V
+5 V
3
GND
1
GND
1
NC
NC
NC
Si321xM
NC
NC
NC
1.3. ProSLIC Evaluation Board Setup
To prepare the ProSLIC evaluation board for use,
perform the following steps:
1. Set power supplies to 3.3 V, 5 V, and 12 V.
2. With these supplies off, connect them to J3 and J4
corresponding to the silk screen designators.
3. Connect the PC’s parallel port (LPT1) to P1 (or J1)
using a 25-pin D male-to-male cable.
4. Select the on-board PCM clock source, or select an
external PCM source, and connect an Audio
Precision SIA-2322 to P2 and P3 or a Wandel and
Goltermann PCM-4 to J8, J9, J10, and J11.
5. TIP/RING connection can be made from the RJ-11 to
a phone or telephony test equipment.
6. Invoke the ProSLIC LINC software.
7. Turn the power supplies on and press the ProSLIC
evaluation board reset button (S1).
8. Click the “Reinitialize” button in the ProSLIC LINC
software panel
The ProSLIC is now ready to perform its linecard
function.
Notes:
1.
All three GND connection points are electrically
connected on the board.
2.
+3.3 V is only necessary if that is the desired VDD for
operation. Si321x chooses +3.3 V or +5 V based on
the SP1 of the motherboard (see schematic).
3.
This may be changed based on application-specific
circuits. Consult the dc-dc converter spreadsheet for
other possible values.
Table 3. On-Board PCLK Settings (S2)
S2-1,2,3
PCLK frequency
0,0,0 = 8.192 MHz
0,0,1 = 4.096 MHz
0,1,0 = 2.048 MHz
0,1,1 = 1.024 MHz
1,x,x = 512 kHz
Note:
1 = on.
S2-4
Unused
x
S2-5
Unused
x
S2-6
Unused
x
S2-7
Unused
x
S2-8
FS enable
0 = FS disabled
1 = FS enabled
Table 4. JP1–4 Settings
Jumper
JP1
JP2
JP3
JP4
Function
VDD Level Select
VPCM Level Select
FSYNC Level Select
PCLK Source Select
Jumper Location
1–2
+3 V
+3 V
Internal
Internal
2–3
+5 V
+5 V
External
External
Default Factory
Setting
1–2
2–3
1–2
1–2
Rev. 1.2
3
Si321xPPQx-EVB
Table 5. Audio Precision SIA-2322 DIP Switch Setting
Receiver Mode
00111001
00000010
11111101
01111001
0000001
Transmitter Mode
00000010
11111101
01111001
Note:
256 kHz PCLK and 8 kHz FS.
Table 6. Wandel and Goltermann PCM-4 Settings
General Configuration
General Configuration
General Configuration
For µ-law Add the Following:
General Configuration
General Configuration
7.12
7.22
2.14
3.13
4.13
4
Rev. 1.2
PCM Bus
VCC
+VDC
L2
/RESET
R26
PCLK
DRX
DTX
FSYNC
PCLK
DRX
DTX
FSYNC
/INT
/CS
SCLK
SDI
SDO
Bus
/RESET
/INT
/CS
Control
SCLK
SDI
SDO
SDITHRU
1
1
1
40.2k
47 uH
150 mA
F1
C15
0.1 uF
500mA
TEST
2
2
1
1
2. Schematics
C30
10 uF
10V
2
C16
0.1 uF
C17
0.1 uF
2
C34
10 uF
10V
28
27
3
2
1
38
37
36
35
34
33
32
31
19
6
23
26
U1
2
TEST
GNDA
GNDD
/RESET
FSYNC
DTX
DRX
PCLK
/INT
/CS
SCLK
SDI
SDO
SDITHRU
VDDA1
VDDA2
VDDD
20
SDCH
R16
RSW
200
C25
10 uF
IGMP
4
R19
RMONH 56.2k
C14
0.1uF
R15
RGM
243
18
SDCL
CFF
C10
0.1uF
Q8
2222
QBATD
Test Point
R17
200
Q9
R3
R8
R9
2222
R4
105k
R5
RBAT
100k
R2
105k
Test Point
L1
LSW
100 uH
Note 4
Test Point
QBAT
FZT953
Q7
D1
DSW
IGMN
5
7
R20
RMONL 56.2k
R18
RVDC
0.68
1/4 W
IREF
8
DCFF
DCDRV
30
29
CAPP
10
ProSLIC
Si3210-FM
SRINGDC
STIPAC
SRINGAC
SRINGE
ITIPP
IRINGN
STIPE
IRINGP
ITIPN
SVBAT
ES1D
Note 5
C9
CBAT
10 uF
CAPM
R14
RREF
40.2k
+
C1
CL
10 uF
10V
+
C2
CM
10 uF
10V
11
STIPDC
12
9
QGND
16
17
15
24
21
13
22
25
14
R1
Localized ground traces
RTAC
470
470
RTDC
200k 200k
RRDC
RRAC
--Single point connection
to ground plane
Rev. 1.2
C3
C4
CTAC CRAC
220 nF 220 nF
NI
NI
C33
NI
R105
100k
C32
C31
R104
90.9k
R102
90.9k
R7
4.02k
R6
4.02k
R28
26.1k
U2
R36
37.4k
C26
CFILT
0.1uF
VCC
+
+
C19
4.7 uF
R29
665K
Test PointTest Point
VCC
TIP
J1
Over V
TIP_ext
TIP
1
2
3
1
2
3
J2
6
5
4
3
2
1
6
5
4
3
2
1
1-2: VCC=3.3V
2-3: VCC=5V
* These component need to be
selected appopriatedly for the
corresponding VDC voltage level.
See the data sheet and the AN45
app note for component value.
RING_ext
RJ-11
RING
RING
Protection
C5
CTC
22 nF
C20
Si3201
C6
CRC
22 nF
1
2
3
4
5
6
7
8
Tip
ITIPP
NC
ITIPN
Ring
IRINGP
VBAT
IRINGN
VBATH
NC
NC
STIPE
GND
SRINGE
VDD
NC
GND
epad
C18
4.7 uF
16
15
14
13
12
11
10
9
0.1 uF
Note 5:
Note 4:
R21
RFILT
15
VBAT
Test Point
Note 3:
Note 2:
Note 1:
D1 = Central Semi CMR1U-02M or equivalent
L1 = Delevan or Sumida SPD127 series or equivalent
see application note for value selection
C30 to be Tantalum or Ceramic
All capacitors are 100V, 20% unless otherwise noted
All resistors are 1/10 W, 1% unless otherwise noted
Si321xPPQx-EVB
Figure 1. Si321x QFN with Si3201 Schematic (1 of 3)
5
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