or product names are trademarks or registered trademarks of their respective holders. The specifications and information herein are subject to change without notice.
The product described herein is subject to continuing development, and applicable specifications and information are subject to change without notice. Such specifica-
tions and information are provided in good faith; actual performance is not guaranteed, as it is dependent on many factors, including the user's system design.
www.latticesemi.com
1
ip1039_01.0
Lattice Semiconductor
Correlator IP Core
General Description
A correlation function determines how closely a data sequence matches a reference, or “coefficient” sequence. A
high correlation value means that the data sequence closely matches the coefficient sequence. A low correlation
value means that the data sequence is dissimilar to the coefficient sequence. The basic correlator equation is given
by:
corr _
win
1
r
k
=
i =0
d
i + k
c
i
k = 0,1,…,num_lags-1
(1)
The terms of the equation are:
•
d
i
– Input data sequence. The Correlator IP core allows the input sequence to be from 1 to 8 bits wide, and either
signed (two’s complement) or unsigned data.
•
c
i
– Coefficient (or code) sequence. In the Correlator IP core, this sequence must be loaded into internal memory
prior to a correlation operation. This sequence is always binary {1,0}; however, the coefficient sequence may rep-
resent either an unsigned sequence {1,0} or a signed sequence {+1,-1}. In the case of a signed coefficient
sequence, a 1 in the sequence represents a value of +1 and a 0 in the sequence represents a value of -1. The d
i
and c
i
inputs must both be of the same type, either signed or unsigned.
•
r
k
– Correlation result output sequence (correlation between d
i
and c
i
inputs).
•
corr_win
– Correlation window. This is the number of elements in the input data sequence over which the corre-
lation function is calculated. This is also referred to as the number of “taps.” For the Correlator IP core this num-
ber is determined by the user when configuring the core. Once selected, the number of data elements (and
coefficient terms) is then fixed at this number for all correlation operations. The number of terms in the coefficient
sequence is always equal to the number of taps (corr_win) specified.
•
num_lags
– Total number of lags for which the correlation is performed. This is also the length of the correlation
result sequence, r
k.
From Equation 1, a correlation operation takes an input data sequence d
i
of length “corr_win” and multiplies each
term in the sequence against the terms of the reference coefficient sequence c
i
, summing the results of all of the
multiplications to produce the result r
k
. The input data sequence is then shifted by one element and the operation is
repeated to produce the next term in the r
k
sequence. This is done “num_lags” times.
In the Correlator IP core, each time a new data term is input to the core, one correlation operation is performed
across “corr_win” data and coefficient terms, producing one result, r. The “k” index in Equation 1 does not apply
since the Correlator always produces one new result when it receives one new data value. Old data beyond the
defined correlation window size is not held in memory.
In addition to the basic correlation function described above, the Correlator IP core can be configured to perform
complex correlations, defined by the equation:
corr _
win
1
r
k
=
i =0
d
i + k
c
i
k = 0,1,…,num_lags-1
(2)
In this case, the data and coefficient input sequences are both complex and each contains a real input sequence
and an imaginary input sequence. For the Correlator IP core, the input data sequence is a sequence of signed
(two’s complement) numbers from 1 to 8 bits wide, and the coefficient sequence is a binary sequence where a
coefficient value of 1 represents +1 and a coefficient value of 0 represents a -1. Equation 2 represents the complex
conjugate of c
i
. The complex conjugate multiplication expressed in Equation 2 is given as:
dc = (d
re
c
re
+ d
im
c
im
) + j(d
im
c
re
- d
re
c
im
)
(3)
2
Lattice Semiconductor
Correlator IP Core
Since the coefficients in a complex correlation are restricted to the values {+1,-1}, the multiplications in Equation 3
simplify to inversions of the d
re
and d
im
terms, and the whole equation reduces to a series of additions and subtrac-
tions. The Correlator IP core performs these inversions and sums the results to produce a new result value r for
each new d
re
and d
im
term input to the core. In this case, the result sequence will have two terms, a real term and
an imaginary term.
Functional Description
The Correlator IP core is composed of the following functional blocks:
•
State Machine
– Controls the flow of data received from the user. Generates the starting pointer values neces-
sary to read/write the Tap Memory and stores the pointer values in the Channel Memory. Stores the starting
pointer values for the next correlation operation in the input FIFO. Generates the “shiftby” value for the aligner.
•
Channel Memory
– Stores the pointer to the location in Tap Memory to write the next data value.
•
Input FIFO
– Stores the pointer to the starting point in Tap and Coefficient Memories for the next correlation.
•
Tap Memory
– Stores the data terms (d
i
).
•
Coefficient Memory
– Stores the coefficient terms (c
i
).
•
Aligner
– Aligns data and coefficients read from memory for the correlation operation.
•
Correlator
– Performs the equivalent of the multiplication operations in Equations 1 and 2.
•
Adder/Accumulator
– Performs the addition and subtraction operations in Equations 1 and 2.
Correlator Input and Output Data
The Correlator IP core accepts a new input data value for a channel and writes that value into Tap Memory. When it
is ready to perform the next correlation operation for that channel, the new data value will be included in the corre-
lation, along with enough “old” data already in memory to completely fill the correlation window. The Tap Memory is
a circular buffer which contains a correlation window’s worth of data. As each new value is added to Tap Memory
for a particular channel, a correlation operation needs to be run and completed before the next new value is added
to memory for that channel. New data can be written into Tap Memory for channels other than the one the Correla-
tor is operating on, however it is the user’s responsibility to insure that a correlation operation is done for a particu-
lar channel before new data is written into memory for that same channel. This is easy to do for a large number of
channels where new data is written to channels in a round-robin sequence, or if the Correlator throughput is not
stressed to its limit (i.e. unused cycles appear between correlations), but the problem can be difficult to manage for
small numbers of channels. The Correlator IP core will automatically prevent new data being written into Tap Mem-
ory and corrupting a correlation as long as the input FIFO depth (parameter 9) is set to 1.
Figures 2 and 3 show the timing of the user interface. The state machine accepts one new data value from the user
interface at a time. When the state machine is ready to accept a new input data word from the user interface it
asserts the
crdy
signal. The user interface then inputs
din
,
chan_in
,
code_sel_in
,
block_start_in
, and
asserts the
irdy
signal. When the state machine sees
irdy
go active, it will take the new data value from the user
interface. If the design has been configured for multiple channels, the state machine reads the pointer for that chan-
nel from the Channel Memory. This pointer value tells the state machine where in Tap Memory to write the data
value just received from the user interface. This pointer value will also be the starting point for the next correlation
operation, so this pointer value is stored in the Input FIFO until the next correlation operation is ready to start. Once
the present correlation operation finishes, or if no correlation operation was in progress when a new data value was
received, then the Input FIFO is read to determine the starting pointer for the next correlation. The state machine
begins reading the Tap and Coefficient Memories at the starting pointer location, and it reads until it has read an
entire correlation window’s worth of data and coefficients.
Figure 2 shows at time 173.5µs that
crdy
went active. The user provided a value of 0x3 for channel 0, and set the
code_sel_in
to 1 which indicates which coefficient sequence is to be used for the correlation of channel 0 data.
3
Lattice Semiconductor
Correlator IP Core
In this example, two channels and two different coefficient sequences have been configured. Each channel can be
correlated to either of the two coefficient sequences.
Figure 2. User Interface Timing Diagram for Two-channel Correlator
Figure 3. User Interface Timing Diagram for Two-channel Correlator
The user drives the
irdy
signal high for one clock cycle indicating that the input values are valid. Along with the
input data, the user also sets the
block_start_in
signal. This signal will be taken as a marker by the Correlator
and aligned with the input data as it passes through the Correlator IP core. The next time the
block_start_out
signal is set and
chan_out
= 0, it will indicate that the output data was associated with this input data value. The
block_start
signals act as markers for the user to do frame alignments between the input and outputs of the
Correlator IP core. This is necessary since the core operates on one input data sample at a time. It does not per-
form multiple correlations over “num_lag” values as expressed in Equation 1. This allows the simplest and most
versatile Correlator IP core design. If it is necessary to operate for multiple “lags,” then the user application will
need to add input and output FIFOs around the core to feed data values one sample at time.
At time 178.5µs,
crdy
again goes active indicating that the Correlator IP core is ready to accept the next input
value, and in the example of Figure 2 the user inputs data for channel 1. At time 196.5µs, the correlation result for
channel 0 is ready at the
dout
outputs, and the core outputs a value of 0x9 on
dout
, sets the
chan_out
to 0, and
asserts the
ordy
signal. It also asserts the
block_start_out
signal to indicate that this output value was asso-
ciated with the
din
value from time 175.5µs.
4
Lattice Semiconductor
Figure 4. Tap and Coefficient Memories
Tap Memory
EBR Block
EBR Block
EBR Block
EBR Block
Correlator IP Core
Coefficient Memory
EBR Block
EBR Block
EBR Block
EBR Block
EBR Block
EBR Block
EBR Block
EBR Block
EBR Block
Number
of Data
Words
(Taps)
per Row of Memory = MWIDTH
EBR Block
Number
of Coefficients
per Row of Memory = MWIDTH
Aligner
Correlator
Corr
Cell
Corr
Cell
Corr
Cell
Corr
Cell
Number
of Correlator
Cells = MWIDTH
Tap and Coefficient Memories
While the Tap and Coefficient Memories are being read, the values read are passed to the Aligner. Under the con-
trol of the state machine the Aligner shifts the tap data and coefficients to be passed to the Correlator block. The
state machine also generates strobe signals to the Aligner which indicate, in any given clock cycle, which tap and
coefficient values are valid for the correlator block to work on.
The Tap and Coefficient Memories are implemented with EBR blocks as shown in Figure 4. The Correlator IP core
will automatically configure and instantiate the proper number of EBR blocks in the design based on the parame-
ters selected by the user. In the case of the Tap Memory, the number of correlator cells, number of taps, number of
channels, and the oversampling rate all determine how many EBR memories are needed. The number of correlator
cells (parameter MWIDTH) determines how many words of data can be operated on during a single clock cycle.
The more correlator cells which are configured, the more multiplication operations can occur in a clock cycle and
the overall data throughput goes up. At least one EBR memory is required to feed each correlator cell. All Tap
Memory EBR blocks in the design will be configured to be at least the word width of the input data (DWIDTH) wide.
The EBR blocks can be sized 1, 2, 4, or 9 bits wide, and must be equal to or greater than DWIDTH. Since each
EBR block can store 8192 bits, if the value of [TAP_EBR_WIDTH * (NUM_TAP / MWIDTH) * NUM_CHAN *
OS_FACTOR] exceeds 8192 bits, then multiple EBR blocks will be stacked in columns to feed the correlator cells,
as shown in Figure 4. TAP_EBR_WIDTH is the minimum allowed EBR width which is at least DWIDTH wide. The
Tap Memory EBRs will be configured automatically for the user; however, the user is responsible for determining
the total number of EBR blocks needed for the design and insure that the target LatticeEC™ device contains
enough memories.
The Coefficient Memories are also implemented in EBR blocks. Since each coefficient is constrained to be 1 bit,
the total amount of memory required for coefficients is generally less than that required for tap data. Each EBR
消费电子
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
