CYV15G0404DXB Evaluation Board Users Guide
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
,
CA 95134
•
408-943-2600
Revised October 4, 2004
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CYV15G0404DXB Evaluation Board
Users Guide
TABLE OF CONTENTS
1.0 OVERVIEW ...................................................................................................................................... 5
2.0 KIT CONTENTS ............................................................................................................................... 5
3.0 FEATURES OF THE CYV15G0404DXB ......................................................................................... 5
4.0 FUNCTIONAL DESCRIPTION OF CYV15G0404DXB .................................................................... 6
4.0 CYV15G0404DXB TRANSCEIVER LOGIC BLOCK DIAGRAM ..................................................... 6
5.0 BOARD PHOTOGRAPH AND PIN DESCRIPTIONS .................................................................... 10
6.0 ADJUSTING SETTINGS ON THE BOARD ................................................................................... 17
6.1 Speed Select Jumpers .............................................................................................................. 17
6.2 DIP Switches ............................................................................................................................. 17
6.3 Asserting Values to Control Latches ......................................................................................... 17
6.4 Reference Clock Input Options ................................................................................................. 18
7.0 TEST MODES ................................................................................................................................ 19
7.1 BIST Test Set-up ...................................................................................................................... 19
7.1.1 Single Channel BIST Set-up ........................................................................................................... 19
7.1.1.1 Equipment Required .................................................................................................................................... 19
7.1.1.2 Test Equipment Set-up ................................................................................................................................ 20
7.1.1.3 Test Set-up .................................................................................................................................................... 20
7.1.1.4 External Loopback Mode ............................................................................................................................. 21
7.1.2 Four Channel BIST Set-up with Global Enable ............................................................................... 22
7.1.2.1 Equipment Required .................................................................................................................................... 22
7.1.2.2 Test Set-up .................................................................................................................................................... 22
7.2 Parallel Data Test Mode ........................................................................................................... 23
7.2.1 Equipment Required ....................................................................................................................... 23
7.2.2 Parallel Data Test Set-up ................................................................................................................ 24
7.2.2.1 Encoder Enable Mode .................................................................................................................................. 24
7.2.2.2 Encoder Bypass Mode ................................................................................................................................. 25
7.3 Reclocker Test Mode ................................................................................................................ 27
7.3.1 Equipment Required ....................................................................................................................... 27
7.3.2 Test Equipment Set-up ................................................................................................................... 28
7.3.3 Test Set-up ...................................................................................................................................... 28
APPENDIX A: Schematic Diagram of CYV15G0404DXB Evaluation Board .................................... 30
APPENDIX B: PCB Layout for CYV15G0404DXB Evaluation Board ................................................ 38
APPENDIX C: Bill Of Material (BOM) CYV15G0404DXB Evaluation Board .................................... 55
Page 2 of 56
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CYV15G0404DXB Evaluation Board
Users Guide
LIST OF FIGURES
Figure 4-1. CYV15G0404DXB Block Diagram ........................................................................................ 6
Figure 4-2. Transmit Path Block Diagram................................................................................................ 7
Figure 4-3. Receive Path Block Diagram................................................................................................. 8
Figure 4-4. Device Configuration Control Block Diagram ........................................................................ 9
Figure 5-1. Photograph of Board with Numbering of Connectors .......................................................... 10
Figure 5-2. Channel A Connectors ........................................................................................................ 11
Figure 5-3. Optical Interface Signals ..................................................................................................... 13
Figure 5-4. JTAG Interface Signals ....................................................................................................... 13
Figure 6-1. Speed Select Control with Jumpers .................................................................................... 17
Figure 6-2. Controlling Dip Switch Settings ........................................................................................... 17
Figure 6-3. Write Enable and Reset Buttons ......................................................................................... 17
Figure 6-4. Top View of REFCLK Connectors....................................................................................... 18
Figure 7-1. BIST Mode Operation.......................................................................................................... 19
Figure 7-2. Pictorial Representation of the Internal BIST Set-up........................................................... 20
Figure 7-3. The Eye Diagram through the Signal Analyzer ................................................................... 21
Figure 7-4. SMA Connectors for External Loopback Mode ................................................................... 22
Figure 7-5. Loop Enable, Use Local Clock, and Input Select DIP Switches .......................................... 22
Figure 7-6. Optical Connector for External Loopback Mode.................................................................. 22
Figure 7-7. Loop Enable, Use Local Clock, and Input Select DIP Switches .......................................... 22
Figure 7-8. Generated Clock, Data and Control Signals for Encoded Mode from DG2020 .................. 24
Figure 7-9. Generated Clock and Data Signals for Encoder Bypass Mode from DG2020 .................... 25
Figure 7-10. Pictorial Representation of the Reclocker Test Equipment Set-up ................................... 28
Page 3 of 56
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CYV15G0404DXB Evaluation Board
Users Guide
LIST OF TABLES
Table 5-1. Description of Connectors of the CYV15G0404DXB Evaluation Board .............................
Table 5-2. Description of External Control Pins for Connectors J31 to J41 .........................................
Table 5-3. Device Control Latch Description .......................................................................................
Table 5-4. Device Control Latch Configuration ....................................................................................
Table 6-1. Device Control Latch Configuration Example .....................................................................
Table 7-1. Device Control Latch Configuration for BIST on Channel A ...............................................
Table 7-2. Device Control Latch Configuration Table for Global Configuration ...................................
Table 7-3. Device Control Latch Configuration for Parallel Data Test Mode .......................................
Table 7-4. Input Register Bit Assignments ..........................................................................................
Table 7-5. Output Register Bit Assignments ........................................................................................
Table 7-6. Device Control Latch Configuration for Parallel Data Test Mode, Unencoded ...................
Table 7-7. Device Control Latch Configuration for Bist on Channel A .................................................
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Page 4 of 56
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CYV15G0404DXB Evaluation Board
Users Guide
1.0
Overview
The CYV15G0404DXB Quad Independent-Channel HOTLink II™ Transceiver is a point-to-point or point-to-multipoint communi-
cations building block that allows the transfer of data over high-speed serial links (optical fiber, balanced, and unbalanced copper
transmission lines) at signaling speeds ranging from 195–1500 MBaud per serial link. The independence of each channel
provides the ability to simultaneously transport different types of data at different signaling rates across multiple channels.
This user’s guide describes the operation and interface of the CYV15G0404DXB evaluation board. The evaluation board allows
users to become familiar with the functionality of the CYV15G0404DXB.
2.0
Kit Contents
• CYV15G0404DXB-EVAL (the evaluation board)
•
Dear Customer
letter
• A CD containing
— CYV15G0404DXB data sheet
— CYV15G0404DXB Evaluation Board User’s Guide
— CYV15G0404DXB application notes
— 0404EN.PDA and 0404BYP.PDA files for the DG2020 parallel data generator
— BSDL model
3.0
Features of the CYV15G0404DXB
• Quad channel transceiver for 195- to 1500-MBaud serial signaling rate
— Aggregate throughput of up to 12 Gbits/second
• Second-generation HOTLink
®
technology
• Compliant with multiple standards
—
ESCON
®
, DVB-ASI, SMPTE 292M, SMPTE 259M, Fibre Channel and Gigabit Ethernet (GbE) (IEEE802.3z)
— 8B/10B coded data or 10 bit uncoded data
• Truly independent channels
— Each channel can perform reclocker function
— Each channel can operate at a different signaling rate
— Each channel can transport a different type of data
• Selectable input/output clocking options
• Internal phase-locked loops (PLLs) with no external PLL components
• Selectable differential PECL-compatible serial inputs per channel
— Internal DC-restoration
• Redundant differential PECL-compatible serial outputs per channel
—
Source matched for 50Ω transmission lines
— No external bias resistors required
— Signaling-rate controlled edge-rates
• MultiFrame™ Receive Framer provides alignment options
— Bit and byte alignment
— Comma or Full K28.5 detect
— Single or Multi-byte Framer for byte alignment
— Low-latency option
• Synchronous LVTTL parallel interface
• JTAG boundary scan
• Built-In Self-Test (BIST) for at-speed link testing
Page 5 of 56
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