High Speed Converter Evaluation Platform
HSC-ADC-EVALC
FEATURES
Xilinx Virtex-4 FPGA-based buffer memory board
Used for capturing digital data from high speed ADC
evaluation boards to simplify evaluation
64 kB FIFO depth
Parallel input at 644 MSPS SDR and 800 MSPS DDR
Supports 1.8 V, 2.5 V, and 3.3 V CMOS and LVDS interfaces
Supports multiple ADC channels up to 18 bits
Measures performance with VisualAnalog
Real-time FFT and time domain analysis
Analyzes SNR, SINAD, SFDR, and harmonics
Simple USB port interface (2.0)
Supports ADCs with serial port interfaces (SPI)
FPGA reconfigurable via JTAG, on-board EPROM, or USB
On-board regulator circuit speeds setup
5 V, 3 A switching power supply included
Compatible with Windows 98 (2nd edition), Windows 2000,
Windows ME, and Windows XP
PRODUCT HIGHLIGHTS
1.
Easy to Set Up. Connect the included power supply along
with the CLK and AIN signal sources to the two evaluation
boards. Then connect to the PC via the USB port and
evaluate the performance instantly.
USB Port Connection to PC. PC interface is via a USB 2.0
connection (1.1 compatible) to the PC. A USB cable is
provided in the kit.
64 kB FIFO. The on-board FPGA contains an integrated
FIFO to store data captured from the ADC for subsequent
processing.
Up to 644 MSPS SDR/800 MSPS DDR Encode Rates on
Each Channel. Multichannel ADCs with encode rates up
to 644 MSPS SDR and 800 MSPS DDR can be used with
the ADC capture board.
Supports ADCs with Serial Port Interface or SPI. Some
ADCs include a feature set that can be changed via the
SPI. The ADC capture board supports these SPI-driven
features through the existing USB connection to the
computer without additional cabling needed.
VisualAnalog™. VisualAnalog supports the HSC-ADC-
EVALC hardware platform as well as enabling virtual ADC
evaluation using ADIsimADC™, Analog Devices proprietary
behavioral modeling technology. This allows rapid compari-
son between multiple ADCs, with or without hardware
evaluation boards. For more information, see AN-737 at
www.analog.com/VisualAnalog.
2.
3.
4.
5.
EQUIPMENT NEEDED
Analog signal source and antialiasing filter
Low jitter clock source
High speed ADC evaluation board and ADC data sheet
PC running Windows 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP
Latest version of VisualAnalog
USB 2.0 port recommended (USB 1.1 compatible)
6.
FUNCTIONAL BLOCK DIAGRAM
POWER
CONNECTOR
ON-BOARD
VOLTAGE
REGULATORS
HSC-ADC-EVALC
USB
SINGLE OR MULTICHANNEL
HIGH SPEED ADC
EVALUATION BOARD
LOGIC
FILTERED
ANALOG
INPUT
ADC
n
J3*
FPGA
CONFIGURATION
MODE
DATA BUS 2(18)
CLKA(2)
FPGA
LED2
LED1
UPLOAD
PORTB
PORTD
CAPTURE
DATA(16)
FIFO
CONTROL(9)
J6
USB
CONNECTOR
STANDARD
USB 2.0
ONBOARD
VOLTAGE
J4
REGULATORS
POWER
CONNECTOR
USB
CONTROLLER
PORTC
PORTE
PORTA
n
J2*
DATA BUS 1(18)
CLKB(2)
EXT SYNC1
FPGA
DONE
CLOCK
CIRCUIT
EXT SYNC2
USB
CONFIG
PROM
FPGA
CONFIG
PROM
RECONFIG
SPI
J1*
FPGA GPIO(8)
SPI(7)
USB DIRECT(5)
*DATA CONVERTER I/O CONNECTORS
J10
06676-001
JTAG
CONNECTOR
CLOCK INPUT
Figure 1.
Rev. 0
Evaluation boards are only intended for device evaluation and not for production purposes.
Evaluation boards as supplied “as is” and without warranties of any kind, express, implied, or
statutory including, but not limited to, any implied warranty of merchantability or fitness for a
particular purpose. No license is granted by implication or otherwise under any patents or other
intellectual property by application or use of evaluation boards. Information furnished by Analog
Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog
Devices for its use, nor for any infringements of patents or other rights of third parties that may result
from its use. Analog Devices reserves the right to change devices or specifications at any time
without notice. Trademarks and registered trademarks are the property of their respective owners.
Evaluation boards are not authorized to be used in life support devices or systems.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2007 Analog Devices, Inc. All rights reserved.
HSC-ADC-EVALC
TABLE OF CONTENTS
Features .............................................................................................. 1
Equipment Needed........................................................................... 1
Product Highlights ........................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Product Description......................................................................... 3
Evaluation Board Description......................................................... 3
Evaluation Board Hardware ............................................................ 4
HSC-ADC-EVALC ADC Capture Board Easy Start ............... 4
Power Supplies .............................................................................. 4
Connection and Setup ................................................................. 4
Jumpers .......................................................................................... 5
HSC-ADC-EVALC ADC Capture Board Features.................. 6
HSC-ADC-EVALC Supported ADC Evaluation Boards........ 7
Theory of Operation .........................................................................8
Configuration ................................................................................8
Input Circuitry...............................................................................8
Data Capture ..................................................................................8
Code Description ..........................................................................8
FPGA Configuration and Customization..................................8
Evaluation Board Schematics and Artwork...................................9
HSC-ADC-EVALC Schematics...................................................9
PCB Layout ................................................................................. 23
I/O Connector—J1, J2, and J3 Pin Mapping .......................... 24
Ordering Information.................................................................... 28
Bill of Materials (RoHS Compliant) ........................................ 28
Ordering Guide .......................................................................... 30
ESD Caution................................................................................ 30
REVISION HISTORY
4/07—Revision 0: Initial Version
Rev. 0 | Page 2 of 32
HSC-ADC-EVALC
PRODUCT DESCRIPTION
The Analog Devices, Inc. high speed converter evaluation
platform (HSC-ADC-EVALC) includes the latest version of
VisualAnalog and an FPGA-based buffer memory board to capture
blocks of digital data from the Analog Devices high speed
analog-to-digital converter (ADC) evaluation boards. The ADC
capture board is connected to the PC through a USB port and is
used with VisualAnalog to quickly evaluate the performance of
high speed ADCs. Users can view an FFT for a specific analog
input and encode rate to analyze SNR, SINAD, SFDR, and
harmonic information.
The ADC capture board is easy to set up. Additional equipment
needed includes an Analog Devices high speed ADC evaluation
board, a signal source, and a clock source. Once the kit is
connected and powered, the evaluation is enabled instantly on
the PC.
The ADC capture board enables numerous expansion and
evaluation possibilities by virtue of its powerful reconfigurable
FPGA core.
The system can acquire digital data at speeds up to 644 MSPS
single data rate (SDR) and 800 MSPS double data rate (DDR).
The FPGA contains an integrated FIFO memory that allows
capture of data record lengths up to a total of 64 kB. A USB 2.0
microcontroller communicating with VisualAnalog allows
for easy interfacing to newer computers using the USB 2.0
(USB 1.1 compatible) interface.
EVALUATION BOARD DESCRIPTION
The ADC capture board provides all of the support circuitry
required to accept two 18-bit channels from an ADC’s parallel
CMOS or LVDS outputs. Various functions such as FPGA
configuration load options and I/O logic levels can be selected by
proper connection of various jumpers or switches (see Table 1).
When using the HSC-ADC-EVALC in conjunction with an
ADC evaluation board, it is critical that the signal sources used
for the ADC board’s analog input and clock have very low phase
noise (<1 ps rms jitter) to achieve the ultimate performance of
the converter.
Proper filtering of the analog input signal to remove harmonics
and lower the integrated or broadband noise at the input is also
necessary to achieve the specified noise performance.
See Figure 5 to Figure 20 for complete schematics and layout plots.
Rev. 0 | Page 3 of 32
HSC-ADC-EVALC
EVALUATION BOARD HARDWARE
HSC-ADC-EVALC ADC CAPTURE BOARD
EASY
START
Requirements
•
•
•
•
•
•
•
HSC-ADC-EVALC ADC capture board, VisualAnalog, 5 V
wall transformer, and USB cable
High speed ADC evaluation board and ADC data sheet
Power supply for ADC evaluation board
Analog signal source and appropriate filtering
Low jitter clock source applicable for specific ADC
evaluation, typically <1 ps rms jitter
PC running Windows® 98 (2nd edition), Windows 2000,
Windows ME, or Windows XP
PC with a USB 2.0 port recommended (USB 1.1 compatible)
Once the USB cable is connected to both the computer and
the HSC-ADC-EVALC board, and power is applied, the
USB driver starts to install. The
Found New Hardware
Wizard
opens and prompts you through the automated
install process.
7. (Optional) Verify in the Windows device manager that
Analog Devices ADC-HSC-EVALC
is listed under the
USB hardware.
8. Refer to the instructions included in the respective ADC
data sheet found at
www.analog.com/FIFO
for more
information about connecting the ADC evaluation board’s
power supply and other requirements. After verification of
power supply connections, apply power to the ADC
evaluation board and check the voltage levels on the ADC
board to make sure they are correct.
9. Make sure the evaluation boards are powered on before
connecting the analog input and clock. Connect the
appropriate analog input (which should be filtered with a
band-pass filter) and low jitter clock signal.
10. Refer to the
VisualAnalog User Manual
at
www.analog.com/FIFO
for detailed software operating
instructions.
6.
Easy Start Steps
Important Note
Administrative rights for the Windows operating systems are
needed during the entire easy start procedure.
Completion of every step before reverting to a normal user
mode is recommended.
1.
Install VisualAnalog from the CD provided in the ADC
capture board kit or download the latest version from the
Web. For the latest updates to the software, check the
Analog Devices website at
www.analog.com/FIFO.
Connect the ADC capture board to the ADC evaluation
board. If an adapter is required, insert the adapter between
the ADC evaluation board and the ADC capture board.
Connect the provided USB cable to the ADC capture board
and to an available USB port on the computer.
Refer to Table 1 for setting the ADC capture board’s I/O
logic level to match the level coming from the ADC evalua-
tion board. 1.8 V is default; 2.5 V and 3.3 V are jumper
selectable. Most evaluation boards can be used with the
default settings.
The ADC capture board is supplied with a wall mount
switching power supply. Connect the supply end to an ac
wall outlet rated for 100 Vac to 240 Vac at 47 Hz to 63 Hz.
The other end is a 2.1 mm inner diameter jack that connects
to the PCB at J4.
POWER SUPPLIES
The ADC capture board is supplied with a wall mount switch-
ing power supply that provides a 5 V, 3 A maximum output.
Connect the supply to the rated 100 Vac to 240 Vac wall outlet at
47 Hz to 63 Hz. The other end is a 2.1 mm inner diameter jack
that connects to the PCB at J4. On the PC board, the supply is
fused and conditioned before connecting to the regulators that
supply the proper bias to the entire ADC capture board.
2.
3.
4.
CONNECTION AND SETUP
The ADC capture board has two 40-pin connectors (J2 and J3)
that accept two 18-bit channels of parallel CMOS or LVDS
inputs from the ADC (see Figure
2
). The third 40-pin connector
(J1) is used to pass SPI and other USB/FPGA control signals
across to adjacent ADC evaluation boards that support these
features.
5.
Rev. 0 | Page 4 of 32
HSC-ADC-EVALC
WALL OUTLET
100V TO 240V AC
47Hz TO 63Hz
ONBOARD POWER
SUPPLY
PS
SWITCHING
POWER
SUPPLY
5V DC
3A MAX
DATA BUS 2
PARALLEL
LVDS/CMOS
OUTPUTS
EVALUATION
BOARD
BAND-PASS
FILTER
XFMR
INPUT
DATA BUS 1
PARALLEL
LVDS/CMOS
OUTPUTS
SPI
–
+
GND
V
REG
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
ROHDE & SCHWARZ,
SMHU,
2V p-p SIGNAL
SYNTHESIZER
HSC-ADC-EVALC
DATA CAPTURE
BOARD
PC
RUNNING
VisualAnalog
USB
CONNECTION
SPI
06676-004
CLK
Figure 2. Example Setup Using ADC Evaluation Board and HSC-ADC-EVALC ADC Capture Board
JUMPERS
Default Settings
Table 1 lists the default settings for the HSC-ADC-EVALC evaluation kit.
Table 1. Jumper Configurations
Jumper Number
J9, Pin 1 to Pin 2 (1.8 V)
J9, Pin 3 to Pin 4 (2.5 V)
J9, Pin 5 to Pin 6 (3.3 V)
Description
Default. Sets FPGA I/O voltage to 1.8 V logic (hardwired, do not remove).
Install single jumper here to set FPGA I/O voltage to 2.5 V logic.
Install single jumper here to set FPGA I/O voltage to 3.3 V logic.
Table 2. FPGA Configuration Mode
U4 DIP Switch Setting
FPGA Configured via EEPROM
FPGA Configured via USB (Default)
M0
On
On
M1
On
Off
M2
On
Off
M3
Reserved
Reserved
M4
Reserved
Reserved
Rev. 0 | Page 5 of 32
京公网安备 11010802033920号
Copyright © 2005-2026 EEWORLD.com.cn, Inc. All rights reserved
电子工程世界
