74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output
latches; 3-state
Rev. 7 — 26 January 2015
Product data sheet
1. General description
The 74HC595; 74HCT595 are high-speed Si-gate CMOS devices and are pin compatible
with Low-power Schottky TTL (LSTTL). They are specified in compliance with JEDEC
standard No. 7A.
The 74HC595; 74HCT595 are 8-stage serial shift registers with a storage register and
3-state outputs. The registers have separate clocks.
Data is shifted on the positive-going transitions of the shift register clock input (SHCP).
The data in each register is transferred to the storage register on a positive-going
transition of the storage register clock input (STCP). If both clocks are connected together,
the shift register will always be one clock pulse ahead of the storage register.
The shift register has a serial input (DS) and a serial standard output (Q7S) for cascading.
It is also provided with asynchronous reset (active LOW) for all 8 shift register stages. The
storage register has 8 parallel 3-state bus driver outputs. Data in the storage register
appears at the output whenever the output enable input (OE) is LOW.
2. Features and benefits
8-bit serial input
8-bit serial or parallel output
Storage register with 3-state outputs
Shift register with direct clear
100 MHz (typical) shift out frequency
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115-A exceeds 200 V
Multiple package options
Specified from
40 C
to +85
C
and from
40 C
to +125
C
3. Applications
Serial-to-parallel data conversion
Remote control holding register
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
4. Ordering information
Table 1.
Ordering information
Package
Temperature range
74HC595N
74HCT595N
74HC595D
74HCT595D
74HC595DB
74HCT595DB
74HC595PW
74HCT595PW
74HC595BQ
74HCT595BQ
40 C
to +125
C
DHVQFN16
40 C
to +125
C
TSSOP16
40 C
to +125
C
SSOP16
40 C
to +125
C
SO16
plastic small outline package; 16 leads;
body width 3.9 mm
plastic shrink small outline package; 16 leads;
body width 5.3 mm
plastic thin shrink small outline package; 16 leads;
body width 4.4 mm
plastic dual in-line compatible thermal enhanced
very thin quad flat package; no leads; 16 terminals;
body 2.5
3.5
0.85 mm
SOT109-1
SOT338-1
SOT403-1
SOT763-1
40 C
to +125
C
Name
DIP16
Description
plastic dual in-line package; 16 leads (300 mil)
Version
SOT38-4
Type number
5. Functional diagram
Fig 1.
Functional diagram
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 26 January 2015
2 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
Fig 2.
Logic symbol
Fig 3.
IEC logic symbol
Fig 4.
Logic diagram
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 26 January 2015
3 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6. Pinning information
6.1 Pinning
Fig 5.
Pin configuration DIP16, SO16
Fig 6.
Pin configuration SSOP16, TSSOP16
(1) This is not a supply pin. The substrate is attached to this pad using conductive die attach material. There is no electrical or
mechanical requirement to solder this pad. However, if it is soldered, the solder land should remain floating or be connected to
GND.
Fig 7.
Pin configuration for DHVQFN16
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 26 January 2015
4 of 24
NXP Semiconductors
74HC595; 74HCT595
8-bit serial-in, serial or parallel-out shift register with output latches; 3-state
6.2 Pin description
Table 2.
Symbol
Q1
Q2
Q3
Q4
Q5
Q6
Q7
GND
Q7S
MR
SHCP
STCP
OE
DS
Q0
V
CC
Pin description
Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Description
parallel data output 1
parallel data output 2
parallel data output 3
parallel data output 4
parallel data output 5
parallel data output 6
parallel data output 7
ground (0 V)
serial data output
master reset (active LOW)
shift register clock input
storage register clock input
output enable input (active LOW)
serial data input
parallel data output 0
supply voltage
7. Functional description
Table 3.
Control
SHCP STCP OE
X
X
X
X
X
X
L
L
H
L
MR
L
L
L
H
Function table
[1]
Input
DS
X
X
X
H
Output
Q7S
L
L
L
Q6S
Qn
NC
L
Z
NC
a LOW-level on MR only affects the shift registers
empty shift register loaded into storage register
shift register clear; parallel outputs in high-impedance OFF-state
logic HIGH-level shifted into shift register stage 0. Contents of all
shift register stages shifted through, e.g. previous state of stage 6
(internal Q6S) appears on the serial output (Q7S).
contents of shift register stages (internal QnS) are transferred to
the storage register and parallel output stages
contents of shift register shifted through; previous contents of the
shift register is transferred to the storage register and the parallel
output stages
Function
X
L
L
H
H
X
X
NC
Q6S
QnS
QnS
[1]
H = HIGH voltage state;
L = LOW voltage state;
= LOW-to-HIGH transition;
X = don’t care;
NC = no change;
Z = high-impedance OFF-state.
74HC_HCT595
All information provided in this document is subject to legal disclaimers.
© NXP Semiconductors N.V. 2015. All rights reserved.
Product data sheet
Rev. 7 — 26 January 2015
5 of 24
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