Fully asynchronous and simultaneous read and write
operation
Empty, Full, Half Full, and programmable Almost Empty
and Almost Full status flags
Retransmit function
Output Enable (OE) pin
Independent read and write enable pins
Supports free-running 50% duty cycle clock inputs
Width Expansion Capability
Depth Expansion Capability
68-pin PLCC and 64-pin 10x10 STQFP
Pin-compatible density upgrade to
CY7C42X5V-JC/ASC families
Pin-compatible 3.3V solutions for CY7C4255/65/75/85
D
0 – 17
Functional Description
The CY7C4255/65/75/85V are high-speed, low-power, first-in
first-out (FIFO) memories with clocked read and write interfac-
es. All are 18 bits wide and are pin/functionally compatible to
the
CY7C42X5V Synchronous FIFO
family. The
CY7C4255/65/75/85V can be cascaded to increase FIFO
depth. Programmable features include Almost Full/Almost
Empty flags. These FIFOs provide solutions for a wide variety of
data buffering needs, including high-speed data acquisition, multipro-
cessor interfaces, and communications buffering.
These FIFOs have 18-bit input and output ports that are con-
trolled by separate clock and enable signals. The input port is
controlled by a free-running clock (WCLK) and a write enable
pin (WEN).
When WEN is asserted, data is written into the FIFO on the rising
edge of the WCLK signal. While WEN is held active, data is continu-
ally written into the FIFO on each cycle. The output port is controlled
in a similar manner by a free-running read clock (RCLK) and a read
enable pin (REN). In addition, the CY7C4255/65/75/85V have an
output enable pin (OE). The read and write clocks may be tied togeth-
er for single-clock operation or the two clocks may be run indepen-
dently for asynchronous read/write applications. Clock frequencies
up to 67 MHz are achievable.
Retransmit and Synchronous Almost Full/Almost Empty flag
features are available on these devices.
Depth expansion is possible using the cascade input (WXI,
RXI), cascade output (WXO, RXO), and First Load (FL) pins. The
WXO and RXO pins are connected to the WXI and RXI pins of the
next device, and the WXO and RXO pins of the last device should be
connected to the WXI and RXI pins of the first device. The FL pin of
the first device is tied to V
SS
and the FL pin of all the remaining devic-
es should be tied to V
CC
.
Logic Block Diagram
INPUT
REGISTER
WCLK
WEN
WRITE
CONTROL
High
Density
Dual-Port
RAM Array
8Kx9
16Kx9
32Kx9
64Kx9
FLAG
PROGRAM
REGISTER
FLAG
LOGIC
FF
EF
PAE
PAF
SMODE
WRITE
POINTER
READ
POINTER
RS
RESET
LOGIC
FL/RT
WXI
WXO/HF
RXI
RXO
EXPANSION
LOGIC
THREE–STATE
OUTPUT REGISTER
OE
READ
CONTROL
4275V–1
Q
0 – 17
RCLK
REN
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
• CA 95134 •
408-943-2600
November 6, 1997 - Revised February 26, 1998
PRELIMINARY
Pin Configurations
PLCC
Top View
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
STQFP
Top View
9 8 7
D
14
D
13
D
12
D
11
D
10
D
9
V
CC
D
8
GND
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
6 5
4
3 2 1 68 67 66 65 64 63 62 61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
V
CC
/SMODE
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
V
CC
Q
6
Q
5
GND
Q
4
D
15
D
14
D
13
D
12
D
11
D
10
D
9
D
8
D
7
D
6
D
5
D
4
D
3
D
2
D
1
D
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Q
14
Q
13
GND
Q
12
Q
11
V
CC
Q
10
Q
9
GND
Q
8
Q
7
Q
6
Q
5
GND
Q
4
V
CC
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
CY7C4255V
CY7C4265V
CY7C4275V
CY7C4285V
2728 2930 3132 33 34 35 36 37 38 3940
4142 43
4275V–3
4275V–2
Functional Description
(continued)
The CY7C4255/65/75/85V provides five status pins. These pins are
decoded to determine one of five states: Empty, Almost Empty, Half
Full, Almost Full, and Full (see
Table 2).
The Half Full flag shares the
WXO pin. This flag is valid in the stand-alone and width-expansion
configurations. In the depth expansion, this pin provides
the expansion out (WXO) information that is used to signal
the next FIFO when it will be activated.
The Empty and Full flags are synchronous, i.e., they change
state relative to either the read clock (RCLK) or the write clock
(WCLK). When entering or exiting the Empty states, the flag is
updated exclusively by the RCLK. The flag denoting Full states
is updated exclusively by WCLK. The synchronous flag archi-
tecture guarantees that the flags will remain valid from one
clock cycle to the next. The Almost Empty/Almost Full flags
become synchronous if the V
CC
/SMODE is tied to V
SS
. All
configurations are fabricated using an advanced 0.35µ
CMOS technology. Input ESD protection is greater than
2001V, and latch-up is prevented by the use of guard rings.
Selection Guide
7C4255/65/75/85V–15
Maximum Frequency (MHz)
Maximum Access Time (ns)
Minimum Cycle Time (ns)
Minimum Data or Enable Set-Up (ns)
Minimum Data or Enable Hold (ns)
Maximum Flag Delay (ns)
Active Power Supply
Current (I
CC1
) (mA)
Commercial
Industrial
66.7
10
15
4
0
10
30
35
7C4255/65/75/85V–25
40
15
25
6
1
15
30
CY7C4255V
Density
Package
8K x 18
64-pin 10x10 TQFP
68-pin PLCC
CY7C4265V
16K x 18
64-pin 10x10 TQFP
68-pin PLCC
CY7C4275V
32K x 18
64-pin 10x10 TQFP
68-pin PLCC
CY7C4285V
64K x 18
64-pin 10x10 TQFP
68-pin PLCC
2
PRELIMINARY
Pin Definitions
Signal Name
D
0–17
Q
0–17
WEN
REN
WCLK
Description
Data Inputs
Data Outputs
Write Enable
Read Enable
Write Clock
I/O
I
O
I
I
I
Data inputs for an 18-bit bus.
Data outputs for an 18-bit bus.
Enables the WCLK input.
Enables the RCLK input.
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Function
The rising edge clocks data into the FIFO when WEN is LOW and the FIFO is not
Full. When LD is asserted, WCLK writes data into the programmable flag-offset
register.
The rising edge clocks data out of the FIFO when REN is LOW and the FIFO is not
Empty. When LD is asserted, RCLK reads data out of the programmable flag-off-
set register.
Dual-Mode Pin:
Single device or width expansion – Half Full status flag.
Cascaded – Write Expansion Out signal, connected to WXI of next device.
When EF is LOW, the FIFO is empty. EF is synchronized to RCLK.
When FF is LOW, the FIFO is full. FF is synchronized to WCLK.
When PAE is LOW, the FIFO is almost empty based on the almost-empty offset
value programmed into the FIFO. PAE is asynchronous when V
CC
/SMODE is tied
to V
CC
; it is synchronized to RCLK when V
CC
/SMODE is tied to V
SS
.
When PAF is LOW, the FIFO is almost full based on the almost full offset value
programmed into the FIFO. PAF is asynchronous when V
CC
/SMODE is tied to
V
CC
; it is synchronized to WCLK when V
CC
/SMODE is tied to V
SS
.
When LD is LOW, D
0–17
(Q
0–17
) are written (read) into (from) the programma-
ble-flag-offset register.
Dual-Mode Pin:
Cascaded – The first device in the daisy chain will have FL tied to V
SS
; all other
devices will have FL tied to V
CC
. In standard mode or width expansion, FL is tied
to V
SS
on all devices.
Not Cascaded – Tied to V
SS
. Retransmit function is also available in stand-alone
mode by strobing RT.
Cascaded – Connected to WXO of previous device.
Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXO of previous device.
Not Cascaded – Tied to V
SS
.
Cascaded – Connected to RXI of next device.
Resets device to empty condition. A reset is required before an initial read or write
operation after power-up.
When OE is LOW, the FIFO’s data outputs drive the bus to which they are con-
nected. If OE is HIGH, the FIFO’s outputs are in High Z (high-impedance) state.
Dual-Mode Pin
Asynchronous Almost Empty/Almost Full flags – tied to V
CC
.
Synchronous Almost Empty/Almost Full flags – tied to V
SS
.
(Almost Empty synchronized to RCLK, Almost Full synchronized to WCLK.)
RCLK
Read Clock
I
WXO/HF
Write Expansion
Out/Half Full Flag
Empty Flag
Full Flag
Programmable
Almost Empty
Programmable
Almost Full
Load
First Load/
Retransmit
O
EF
FF
PAE
O
O
O
PAF
O
LD
FL/RT
I
I
WXI
RXI
RXO
RS
OE
V
CC
/SMODE
Write Expansion
Input
Read Expansion
Input
Read Expansion
Output
Reset
Output Enable
Synchronous
Almost Empty/
Almost Full Flags
I
I
O
I
I
I
3
PRELIMINARY
Maximum Ratings
(Above which the useful life may be impaired. For user guide-
lines, not tested.)
Storage Temperature ................................–65
°
C to +150
°
C
Ambient Temperature with
Power Applied ............................................–55
°
C to +125
°
C
Supply Voltage to Ground Potential .........–0.5V to V
CC
+0.5V
DC Voltage Applied to Outputs
in High Z State .........................................–0.5V to V
CC
+0.5V
DC Input Voltage
..........................................−0.5V
to V
CC
+0.5V
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
Output Current into Outputs (LOW)............................. 20 mA
Static Discharge Voltage ........................................... >2001V
(per MIL–STD–883, Method 3015)
Latch-Up Current..................................................... >200 mA
Operating Range
Range
Commercial
Industrial
[1]
Ambient
Temperature
0
°
C to +70
°
C
–40
°
C to +85
°
C
V
CC
3.3V +300mV
and
−600mV
3.3V
+300mV
and
−600mV
Electrical Characteristics
Over the Operating Range
[2]
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Parameter
V
OH
V
OL
V
IH [3]
V
IL [3]
I
IX
I
OZL
I
OZH
I
CC1[4]
I
SB[5]
Description
Output HIGH Voltage
Output LOW Voltage
Input HIGH Voltage
Input LOW Voltage
Input Leakage
Current
Output OFF,
High Z Current
Active Power Supply
Current
Average Standby
Current
V
CC
= Max.
OE > V
IH
,
V
SS
< V
O
< V
CC
Com’l
Ind
Com’l
Ind
Test Conditions
V
CC
= Min., I
OH
= –1.0 mA
V
CC
= 3.0V. I
OH
= –2.0 mA
V
CC
= Min.,I
OL
= 4.0 mA
V
CC
= 3.0V.,I
OL
= 8.0 mA
2.0
–0.5
–10
–10
Min.
2.4
0.4
V
CC
0.8
+10
+10
30
35
3
3
3
2.0
–0.5
–10
–10
Max.
Min.
2.4
0.4
V
CC
0.8
+10
+10
30
Max.
Unit
V
V
V
V
µA
µA
mA
mA
mA
mA
Capacitance
[6]
Parameter
C
IN
C
OUT
Description
Input Capacitance
Output Capacitance
Test Conditions
T
A
= 25
°
C, f = 1 MHz,
V
CC
= 3.3V
Max.
5
7
Unit
pF
pF
Notes:
1. T
A
is the “instant on” case temperature.
2. See the last page of this specification for Group A subgroup testing information.
3. The V
IH
and V
IL
specifications apply for all inputs except WXI, RXI. The WXI, RXI pin is not a TTL input. It is connected to either RXO, WXO of the
previous device or V
SS
.
4. Input signals switch from 0V to 3V with a rise/fall time of less than 3 ns, clocks and clock enables switch at 20 MHz, while data inputs switch at 10MHz. Outputs
are unloaded.
5. All inputs = V
CC
– 0.2V, except RCLK and WCLK (which are at frequency = 0 MHz), and FL/RT which is at V
SS
. All outputs are unloaded.
6. Tested initially and after any design changes that may affect these parameters.
4
PRELIMINARY
AC Test Loads and Waveforms
[7, 8]
R1=330Ω
3.3V
OUTPUT
C
L
INCLUDING
JIG AND
SCOPE
R2=510Ω
3.0V
GND
≤
3 ns
4285V–4
CY7C4255V/CY7C4265V
CY7C4275V/CY7C4285V
ALL INPUT PULSES
90%
10%
90%
10%
≤
3 ns
4275V–5
Equivalent to:
THÉVENIN EQUIVALENT
200
Ω
OUTPUT
2.0V
Switching Characteristics
Over the Operating Range
7C4255/65/75/85V–15 7C4255/65/75/85V–25
Parameter
t
S
t
A
t
CLK
t
CLKH
t
CLKL
t
DS
t
DH
t
ENS
t
ENH
t
RS
t
RSR
t
RSF
t
PRT
t
RTR
t
OLZ
t
OE
t
OHZ
t
WFF
t
REF
t
PAFasynch
t
PAFsynch
t
PAEasynch
Description
Clock Cycle Frequency
Data Access Time
Clock Cycle Time
Clock HIGH Time
Clock LOW Time
Data Set-Up Time
Data Hold Time
Enable Set-Up Time
Enable Hold Time
Reset Pulse Width
[9]
Reset Recovery Time
Reset to Flag and Output Time
Retransmit Pulse Width
Retransmit Recovery Time
Output Enable to Output in Low Z
[10]
Output Enable to Output Valid
Output Enable to Output in High Z
[10]
Write Clock to Full Flag
Read Clock to Empty Flag
Clock to Programmable Almost-Full Flag
[11]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
Clock to Programmable Almost-Full Flag
(Synchronous mode, V
CC
/SMODE tied to V
SS
)
Clock to Programmable Almost-Empty Flag
[11]
(Asynchronous mode, V
CC
/SMODE tied to V
CC
)
60
90
0
3
3
10
8
10
10
16
10
16
2
15
6
6
4
0
4
0
15
10
15
60
90
0
3
3
12
12
15
15
20
15
20
Min.
Max.
66.7
10
2
25
10
10
6
1
6
1
25
15
25
Min.
Max.
40
15
Unit
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Notes:
7. C
L
= 30 pF for all AC parameters except for t
OHZ
.
8. C
L
= 5 pF for t
OHZ
.
9. Pulse widths less than minimum values are not allowed.
10. Values guaranteed by design, not currently tested.
11. t
PAFasynch
, t
PAEasynch
, after program register write will not be valid until 5 ns + t
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