CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 multiplexer/demultiplexer
switch for PCI Express Gen2
Rev. 1 — 10 March 2011
Product data sheet
1. General description
CBTL02042A/B is a 2 differential channel, 2-to-1 multiplexer/demultiplexer switch for PCI
Express Generation 2 (Gen2), and other high-speed serial interface applications. The
CBTL02042A/B can switch two differential signals to one of two locations. Using a unique
design technique, NXP has minimized the impedance of the switch such that the
attenuation observed through the switch is negligible, and also minimized the
channel-to-channel skew as well as channel-to-channel crosstalk, as required by the
high-speed serial interface. CBTL02042A/B allows expansion of existing high speed ports
for extremely low power.
The device's pinouts are optimized to match different application layouts. CBTL02042A
has input and output pins on the opposite of the package, and is suitable for edge
connector(s) with different signal sources on the motherboard. CBTL02042B has outputs
on both sides of the package, and the device can be placed between two connectors to
multiplex differential signals from a controller. Please refer to
Section 8
for layout
examples.
2. Features and benefits
2 bidirectional differential channel, 2 : 1 multiplexer/demultiplexer
High-speed signal switching for PCIe Gen2 5 Gbit/s
High bandwidth: 7 GHz at
−3
dB
Low insertion loss:
−0.5
dB at 100 MHz
−1.2
dB at 2.5 GHz
Low intra-pair skew: 5 ps typical
Low inter-pair skew: 35 ps maximum
Low crosstalk:
−30
dB at 2.5 GHz
Low off-state isolation:
−25
dB at 2.5 GHz
Low return loss:
−20
dB at 2.5 GHz
V
DD
operating range: 3.3 V
±
10 %
Shutdown pin (XSD) for power-saving mode
Standby current less than 1
μA
ESD tolerance:
8 kV HBM
1 kV CDM
DHVQFN20 package
NXP Semiconductors
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
3. Applications
Routing of high-speed differential signals with low signal attenuation
PCIe Gen2
DisplayPort 1.2
USB 3.0
SATA 6 Gbit/s
4. Ordering information
Table 1.
Ordering information
Package
Name
CBTL02042ABQ
CBTL02042BBQ
DHVQFN20
DHVQFN20
Description
plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 20 terminals; body 2.5
×
4.5
×
0.85 mm
[1]
plastic dual in-line compatible thermal enhanced very thin quad flat
package; no leads; 20 terminals; body 2.5
×
4.5
×
0.85 mm
[1]
Version
SOT764-1
SOT764-1
Type number
[1]
Total height after printed-circuit board mounting = 1.0 mm maximum.
5. Functional diagram
A0_P
A0_N
A1_P
A1_N
B0_P
B0_N
B1_P
B1_N
C0_P
C0_N
C1_P
C1_N
SEL
XSD
002aaf073
Fig 1.
Functional diagram of CBTL02042A; CBTL02042B
CBTL02042A_CBTL02042B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 10 March 2011
2 of 16
NXP Semiconductors
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
6. Pinning information
6.1 Pinning
CBTL02042A
20 GND
V
DD
terminal 1
index area
XSD
A0_P
A0_N
GND
V
DD
A1_P
A1_N
SEL
2
3
4
5
6
7
8
9
V
DD
10
GND 11
terminal 1
index area
19 B0_P
18 B0_N
17 B1_P
16 B1_N
15 C0_P
14 C0_N
13 C1_P
12 C1_N
A0_P
A0_N
C0_P
C0_N
A1_P
A1_N
C1_P
C1_N
2
3
4
5
6
7
8
9
GND 10
V
DD
11
CBTL02042B
GND
1
20 V
DD
19 XSD
18 B0_P
17 B0_N
16 V
DD
15 GND
14 B1_P
13 B1_N
12 SEL
1
002aaf761
002aaf762
Transparent top view
Transparent top view
a. CBTL02042A
Fig 2.
Pin configuration for DHVQFN20
b. CBTL02042B
6.2 Pin description
Table 2.
Symbol
A0_P
A0_N
A1_P
A1_N
B0_P
B0_N
B1_P
B1_N
C0_P
C0_N
C1_P
C1_N
SEL
Pin description
Pin
CBTL02042A
3
4
7
8
19
18
17
16
15
14
13
12
9
CBTL02042B
2
3
6
7
18
17
14
13
4
5
8
9
12
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
CMOS
single-ended
input
channel 0, port A differential signal
input/output
channel 1, port A differential signal
input/output
channel 0, port B differential signal
input/output
channel 1, port B differential signal
input/output
channel 0, port C differential signal
input/output
channel 1, port C differential signal
input/output
operation mode select
SEL = LOW: A
↔
B
SEL = HIGH: A
↔
C
Type
Description
CBTL02042A_CBTL02042B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 10 March 2011
3 of 16
NXP Semiconductors
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
Pin description
…continued
Pin
CBTL02042A
CBTL02042B
19
CMOS
single-ended
input
Shutdown pin; should be driven
LOW or connected to V
SS
for
normal operation. When HIGH, all
paths are switched off
(non-conducting high-impedance
state), and supply current
consumption is minimized.
positive supply voltage,
3.3 V (± 10 %)
supply ground
2
Type
Description
Table 2.
Symbol
XSD
V
DD
GND
[1]
1, 6, 10
5, 11, 20,
center pad
11, 16, 20
1, 10, 15,
center pad
power
power
[1]
DHVQFN20 package die supply ground is connected to both GND pins and exposed center pad. GND pins
and the exposed center pad must be connected to supply ground for proper device operation. For
enhanced thermal, electrical, and board level performance, the exposed pad needs to be soldered to the
board using a corresponding thermal pad on the board and for proper heat conduction through the board,
thermal vias need to be incorporated in the printed-circuit board in the thermal pad region.
7. Functional description
Refer to
Figure 1 “Functional diagram of CBTL02042A; CBTL02042B”.
7.1 Function selection and shutdown function
The CBTL02042A/B provides a shutdown function to minimize power consumption when
the application is not active, but power to the CBTL02042A/B is provided. The XSD pin
(active HIGH) places all channels in high-impedance state (non-conducting) while
reducing current consumption to near-zero. When XSD pin is LOW, the device operates
normally.
Table 3.
Function selection
X = Don’t care.
XSD
HIGH
LOW
LOW
SEL
X
LOW
HIGH
Function
An, Bn and Cn pins are high-Z
An to Bn and vice versa
An to Cn and vice versa
CBTL02042A_CBTL02042B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 10 March 2011
4 of 16
NXP Semiconductors
CBTL02042A; CBTL02042B
3.3 V, 2 differential channel, 2 : 1 MUX/deMUX switch for PCIe Gen2
8. Application design-in information
CBTL02042A
eSATA
CONTROLLER
MINI CARD/
mSATA
CONNECTOR
PCIe
CONTROLLER
CBTL02042A
eSATA
CONTROLLER
eSATA/USB 3.0
COMBO
CONNECTOR
USB 3.0
CONTROLLER
002aaf776
Fig 3.
Applications using CBTL02042A
USB 3.0
CONTROLLER
CBTL02042B
USB 3.0
CONNECTOR
USB 3.0
CONNECTOR
002aaf777
Fig 4.
Application using CBTL02042B
CBTL02042A_CBTL02042B
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 1 — 10 March 2011
5 of 16
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