NCP3418, NCP3418A
Dual Bootstrapped 12 V
MOSFET Driver with
Output Disable
The NCP3418 and NCP3418A are dual MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. Each of the drivers is
capable of driving a 3000 pF load with a 25 ns propagation delay and a
20 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal,
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 30 V, with transient voltages as high as 35 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
The NCP3418A is identical to the NCP3418 except that there is no
internal charge pump diode.
The NCP3418 is pin−to−pin compatible with Analog Devices
ADP3418 with the following advantages:
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MARKING
DIAGRAMS
8
8
1
SO−8
D SUFFIX
CASE 751
1
8
8
1
SO−8 EP
PD SUFFIX
CASE 751AC
3418
ALYW
1
1
8
3418A
ALYW
3418
ALYW
1
8
3418A
ALYW
•
•
•
•
•
•
•
•
•
•
•
•
•
Faster Rise and Fall Times
Internal Charge Pump Diode Reduces Cost and Parts Count
Thermal Shutdown for System Protection
Integrated OVP
Internal Pulldown Resistor Suppresses Transient Turn On of Either
MOSFET
Anti Cross−Conduction Protection Circuitry
Floating Top Driver Accommodates Boost Voltages of up to 30 V
One Input Signal Controls Both the Upper and Lower Gate Outputs
Output Disable Control Turns Off Both MOSFETs
Complies with VRM 10.x Specifications
Undervoltage Lockout
Thermal Shutdown
Thermally Enhanced Package Available
A
L
Y
W
= Assembly Location
= Wafer Lot
= Year
= Work Week
PIN CONNECTIONS
BST
IN
OD
V
CC
1
8
DRVH
SW
PGND
DRVL
Features
ORDERING INFORMATION
Device
NCP3418D
NCP3418DR2
NCP3418ADR2
NCP3418ADR2G
NCP3418PD
NCP3418PDR2
Package
SO−8
SO−8
SO−8
SO−8
SO−8 EP
Shipping
†
98 Units/Rail
2500 Tape & Reel
2500 Tape & Reel
2500 Tape & Reel
98 Units/Rail
SO−8 EP 2500 Tape & Reel
NCP3418APDR2 SO−8 EP 2500 Tape & Reel
†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
©
Semiconductor Components Industries, LLC, 2004
1
May, 2004 − Rev. 10
Publication Order Number:
NCP3418/D
NCP3418, NCP3418A
V
CC
4
Not present in
the NCP3418A
1
BST
IN
2
8
100 k
7
Nonoverlap
−
+
1.5 V
−
+
120 k
SW
DRVH
4V
5
DRVL
OD
3
6
PGND
Figure 1. NCP3418/A Block Diagram
PIN DESCRIPTION
Pin
1
Symbol
BST
Description
Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds this
bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value is between
100 nF and 1.0
mF.
An external diode will be needed with the NCP3418A.
Logic−Level Input. This pin has primary control of the drive outputs.
Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
Input Supply. A 1.0
mF
ceramic capacitor should be connected from this pin to PGND.
Output drive for the lower MOSFET.
Power Ground. Should be closely connected to the source of the lower MOSFET.
Switch Node. Connect to the source of the upper MOSFET.
Output drive for the upper MOSFET.
2
3
4
5
6
7
8
IN
OD
V
CC
DRVL
PGND
SW
DRVH
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2
NCP3418, NCP3418A
MAXIMUM RATINGS*
Rating
Operating Ambient Temperature, T
A
Operating Junction Temperature, T
J
(Note 1)
Package Thermal Resistance: SO−8
Junction−to−Case, R
qJC
Junction−to−Ambient, R
qJA
(2−Layer Board)
Package Thermal Resistance: SO−8 EP
Junction−to−Ambient, R
qJA
(Note 2)
Storage Temperature Range, T
S
Lead Temperature Soldering (10 sec): Reflow (SMD styles only)
Standard (Note 3)
Lead Free (Note 4)
SO−8 (240 peak profile)
SO−8 (260 peak profile)
SO−8 EP (240 peak profile)
SO−8 EP (260 peak profile)
Value
0 to 85
0 to 150
45
123
Unit
°C
°C
°C/W
°C/W
°C/W
°C
°C
50
−65 to 150
240 peak
260 peak
1
1
1
3
JEDEC Moisture Sensitivity Level
−
1. Internally limited by thermal shutdown, 150°C min.
2. Rating applies when soldered to an appropriate thermal area on the PCB.
3. 60 − 180 seconds minimum above 183°C.
4. 60 − 180 seconds minimum above 237°C.
*The maximum package power dissipation must be observed.
NOTE:
This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol
V
CC
BST
Pin Name
Main Supply Voltage Input
Bootstrap Supply Voltage Input
V
MAX
15 V
30 V wrt/PGND
35 V
v
50 ns wrt/PGND
15 V wrt/SW
30 V
BST + 0.3 V
35 V
v
50 ns wrt/PGND
15 V wrt/SW
V
CC
+ 0.3 V
V
CC
+ 0.3 V
V
CC
+ 0.3 V
0V
V
MIN
−0.3 V
−0.3 V wrt/SW
SW
DRVH
Switching Node
(Bootstrap Supply Return)
High−Side Driver Output
−1.0 V DC
−10 V< 200 ns
−0.3 V wrt/SW
DRVL
IN
OD
PGND
NOTE:
Low−Side Driver Output
DRVH and DRVL Control Input
Output Disable
Ground
−0.3 V DC
−2.0 V < 200 ns
−0.3 V
−0.3 V
0V
All voltages are with respect to PGND except where noted.
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3
NCP3418, NCP3418A
NCP3418−SPECIFICATIONS
(Note 5) (V
CC
= 12 V, T
A
= 0°C to +85°C, T
J
= 0°C to +125°C unless otherwise noted.)
Parameter
Supply
Supply Voltage Range
Supply Current
OD Input
Input Voltage High
Input Voltage Low
Input Current
Propagation Delay Time (Note 6)
PWM Input
Input Voltage High
Input Voltage Low
Input Current
High−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times (Note 6)
Propagation Delay (Notes 6 & 7)
Low−Side Driver
Output Resistance, Sourcing Current
Output Resistance, Sinking Current
Transition Times
Propagation Delay
Undervoltage Lockout
UVLO
Hysteresis
Thermal Shutdown
Over Temperature Protection
Hysteresis
5.
6.
7.
8.
−
(Note 8)
(Note 8)
150
170
20
°C
°C
−
−
−
(Note 8)
3.9
4.3
0.5
4.6
V
V
−
−
t
rDRVL
t
fDRVL
t
pdhDRVL
t
pdlDRVL
V
CC
= 12 V (Note 8)
V
CC
− V
SW
= 12 V (Note 8)
C
LOAD
= 3.0 nF, See Figure 3
See Figure 3
−
−
−
−
−
−
1.8
1.0
16
11
30
20
3.0
2.5
25
15
60
30
W
W
ns
ns
ns
ns
−
−
t
rDRVH
t
fDRVH
t
pdhDRVH
t
pdlDRVH
V
BST
− V
SW
= 12 V (Note 8)
V
BST
− V
SW
= 12 V (Note 8)
V
BST
− V
SW
= 12 V, C
LOAD
= 3.0 nF,
See Figure 3
V
BST
− V
SW
= 12 V
−
−
−
−
−
−
1.8
1.0
18
10
30
25
3.0
2.5
25
15
60
45
W
W
ns
ns
ns
ns
−
−
−
−
−
−
2.0
−
−1.0
−
−
−
−
0.8
+1.0
V
V
mA
−
−
−
t
pdlOD
t
pdhOD
−
−
−
See Figure 2
2.0
−
−1.0
−
−
−
−
−
40
40
−
0.8
+1.0
60
60
V
V
mA
ns
ns
V
CC
I
SYS
−
BST = 12 V, IN = 0 V
4.6
−
−
2.0
13.2
6.0
V
mA
Symbol
Conditions
Min
Typ
Max
Unit
All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
AC specifications are guaranteed by characterization, but not production tested.
For propagation delays, “t
pdh
’’ refers to the specified signal going high; “t
pdl
’’ refers to it going low.
GBD: Guaranteed by design; not tested in production.
Specifications subject to change without notice.
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4
NCP3418, NCP3418A
OD
t
pdlOD
t
pdhOD
90%
DRVH
or
DRVL
10%
Figure 2. Output Disable Timing Diagram
IN
t
pdlDRVL
t
fDRVL
DRVL
90%
1.5 V
10%
t
pdhDRVH
t
rDRVH
90%
DRVH−SW
90%
t
fDRVH
10%
t
pdlDRVH
t
rDRVL
90%
10%
10%
t
pdhDRVL
SW
4V
Figure 3. Nonoverlap Timing Diagram (timing is referenced to the 90% and 10% points unless otherwise noted)
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