EXSC
–
Embedded & Wirebond Extreme
Temperature Silicon Capacitor
Rev 3.6
Key features
n
Ultra High Operating temperature up to 250°C
n
Low profile (250µm)
n
High stability of capacitance value:
w
Temperature
<1,5%
(-55°C to +250°C)
w
Voltage <0.1%/Volts
w
Negligible capacitance loss through ageing
n
Low leakage current down to 100pA
n
High reliability
n
Aluminum Pad finishing
Thanks to the unique IPDiA Silicon capacitor
technology, most of the problems encountered in
demanding applications can be solved.
Embedded
EXtreme
Temperature
Silicon
Key applications
n
n
n
n
All applications up to 250°C, such as
downhole and defense industries
High reliability applications
Replacement of X8R and C0G dielectrics
Decoupling / Filtering / Charge pump
(i.e.: motor management, temperature
sensors)
Downsizing
n
EXSC provide the highest capacitor
stability
over
the full -55°C/+250°C temperature range in the
market with a
TC<1,5%.
The IPDiA technology offers industry leading
performances relative to
failure rate
with a
FIT<0,017.
This technology also offers
high reliability,
up to
10
times
better
than
alternative
capacitor
Capacitors
are dedicated to applications where
reliability
up to
250°C
is the main parameter.
EXSC are the most appropriate solution for Chip
On Board, Chip On Foil, Chip On Glass, Chip On
Ceramic, flip chip and embedded applications.
This technology features a capacitor integration
capability
(up
to
250nF/mm )
²
technologies, such as Tantalum or MLCC, and
eliminates cracking phenomena.
This Silicon based technology is ROHS compliant
and compatible with lead free reflow soldering
process.
which
offers
capacitance value similar to X8R dielectric, but
with better electrical performances than C0G/NP0
dielectrics, up
to 250°C.
EXSC
Electrical specification
Capacitance value
10
10pF
0.1nF
1nF
Unit
10nF
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1nF/0202/30V
935 125 72C 410
10nF/0202/30V
935 125 72C 510
100nF/0404/11V
935 125 42F 610
100nF/0605/30V
935 125 72G 610
1µF/1208/11V
935 125 42S 710
1µF/1616/30V
935 125 72Y 710
15
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22
Contact
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33
39
47
68
Contact
390pF/0202/30V 470pF/0202/30V 680pF/0202/30V
IPDIA Sales
935 125 72C 339 935 125 72C 347 935 125 72C 368
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33nF/0404/30V
Contact
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935 125 72F 533
IPDIA Sales
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220nF/0505/11V
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935 125 42H 622
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Parameters
Capacitance range
Capacitance tolerances
Operating temperature range
Storage temperatures
Temperature coefficient
Breakdown Voltage (BV)
Capacitance variation versus
RVDC
Equivalent Serial Inductor (ESL)
Equivalent Serial Resistor (ESR)
Insulation resistance
Aging
Reliability
Capacitor height
Value
390pF to 4.7µF
(*)
(*)
±15%
-55 to 250 °C
- 70 to 265 °C
±1,5%,
from -55 to +250°C
30V, 11V
0.1 % /V (from 0 V to RVDC)
Max 100 pH
Max 0.1W
50G
W
min @3V,25°C
10G
W
min @3V,250°C
Negligible, < 0.001% / 10000h
FIT<0.017 parts / billions hours
Max 250µm
(*)
0.1µF
Contact
IPDIA Sales
2.2µF/1612/11V 3.3µF/1616/11V
935 125 42V 722 935 125 42Y 733
4.7µF/2016/11V
935 125 42X 747
(*) Other values on request
Temperature coefficient
PICS vs. MLCC capacitors
Capacitance change (%)
Capacitance change (%)
DC Voltage stability
MLCC capacitors vs. PICS
10
PICS
0
1
1,1
ESL (nH) @25°C
COG(NPO)vs.
vs. PICS
0402 C0G(NPO)
PICS
20
10
0
-10
-20
-30
-40
Y5V
PICS
C0G
X7R
PICS
-10
Capacitance change (%)
Capacitance change (%)
C0G
X8R
C0G
0,9
0,8
0,7
C0G
X8R
-20
-30
X7R
-40
-50
-60
-70
-80
Y5V
X7R
ESL(nH)
Z5U
0,6
0,5
0,4
0,3
0,2
-50
-60
-70
Z5U
Z5U
Temperature (°C)
Y5V
Y5V
PICS
0,1
0
-90
-80
-50
0
50
Temperature (°C)
Temperature (°C)
100
150
200
-100
0
1
2
3
Bias voltage (V)
4
5
6
7
0
50
100
150
200
250
300
350
400
450
500
550
600
650
700
750
800
850
900
950 1000
Capacitance (pF)
Fig.1: Capacitance change versus temperature
variation compared to alternative technologies
Part Number
935.125.
Fig.2 Capacitance change versus voltage
variation compared to alternative
technologies
Fig.3 ESL versus capacitance value
compared to alternative technologies
B.2.
Breakdown
Voltage
4 = 11V
7= 30V
S.
Size
F = 0404
H = 0505
I = 0302
S =1208
V =1216
U
Unit
0 = 10 f
1 = 0.1 p
2=1p
3 = 10 p
4 = 0.1 n
xx
i.e: 100nF/0404
à
935 125 42F 610
Termination
G = 0605
C = 0202
V = 1612
Y = 1616
X = 2016
5=1n
6 = 10 n
7 = 0.1 µ
8=1µ
9 = 10 µ
Value
10
15
22
33
39
47
68
Pad finishing in Aluminum ( 3µm thickness +/-10%).
Applicable for almost all embedded applications.
Parts should be glued with non conductive paste. If conductive glue is used on the backside of the silicon
cap, it is strongly recommended to connect the backside and pads 3&4 to the same level (GND preferred).
Pinning definition & Outline
pin #
1, 2
3, 4
Symbol
Signal
GND
Description
Signal
Ground
Typ.
A
0202
0.58
±0.05
0.58
±0.05
0,15
0,3
0,3
0302
0.80
±0.05
0.64
±0.05
0,15
0,52
0,36
0303
0.80
±0.05
0.80
±0.05
0,15
0,52
0,58
0404
1.00
±0.05
1.00
±0.05
0,15
0,72
0,72
0505
1.25
±0.05
1.25
±0.05
0,15
0,97
0,97
0605
1.50
±0.05
1.25
±0.05
0,15
1,22
1,22
1208
3.00
±0.05
2.00
±0.05
0,15
2,72
1,72
1612
4.00
±0.05
3.00
±0.05
0,15
3,72
2,72
1616
4.00
±0.05
4.00
±0.05
0,15
3,72
3,72
2016
5.00
±0.05
4.00
±0.05
0,15
4,72
3,72
Comp.
size
B
c
d
Packaging
Tape and reel, tray, waffle pack or wafer delivery.
e
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 28 February 2014
Document identifier : CL xxxxxxxxx
th
IPD Capacitor Assembly Set Up
Rev 1.0
Application Note
Outline
Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging
with the following features:
Package dedicated to solve tombstoning effect of small SMD package;
Package compatible with SMD assembly;
Package without underfilling step;
Interconnect available with various optional finishing for specific assembly.
Assembly consideration
Standard pick & place equipment dedicated to WLCSP down to 400µm pitch.
Solder paste type 3 in most cases of EIA size.
Reflow has to be done with standard lead-free profile (for SAC alloys) or
according to JEDEC recommendations J-STD 020D-01.
Lead
Leadfree
Tp: 235 °C
T
L: 183 °C
Ts min: 100 °C
Ts max: 150 °C
t
L
: 60-150 s
Tp: 260 °C
T
L:
217 °C
Ts min: 150 °C
Ts max: 200 °C
t
L
: 60-150 s
Process recommendation
After soldering, no solder paste should touch the side of the capacitor die as that might results in
leakage currents due to remaining flux.
In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder
flux must be cleaned after reflow soldering step.
Notes: for a proper flux cleaning process, “rosin” flux type (R) or “water soluble” flux type (WS) is
recommended for the solder printing material. “No clean” flux (NC) solder paste is not recommended.
In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be
appropriate and the solder volume must be controlled:
- using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a
proper printing process.
- Mirroring pads would be the best recommendation
Application Note
Pad recommendation
The capacitor is compatible with generic requirements for flip chip design (IPC7094).
Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, …).
Die size and land pattern dimensions is set up according to following range :
EIA size
Dimension max(X1 x X2) mm
Typical . die thickness X3 (mm)
Typical pad size* (mm)
Typical pad separation (X4
mm)
0201
0.86x0.66
0402
1.26x0.76
0603
1.86x1.16
0805
2.26x1.46
1206
3.46x1.86
1812
4.76x3.66
0.1 or 0.4
0.15x0.40
0.3
0.30x0.50
0.4
0.40x0.90
0.8
0.50x1.20
1
0.60x1.60
2
0.90x3.40
2.7
X3
X2
X1
Top side
silicon
Typ.UBM thickness
3 to 5 µm
X4
After soldering, no solder paste should touch the side of the capacitor die as that might result in
leakage currents due to remaining flux.
Rev 1.0
2 of 3
Application Note
Manual Handling Considerations
These capacitors are designed to be mounted with a standard SMT line, using solder printing step,
pick and place machine and a final reflow soldering step. In case of manual handling and mounting
conditions, please follow below recommendations:
Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is
recommended).
Use of organic tip instead of metal tip for the nozzle.
Minimize temperature shocks (Substrate pre-heating is recommended).
No wire bonding on 0402 47nF, 0402 100nF, 1206 1 F and 1812 3,3µF
Process steps:
On substrate, form the solder meniscus on each land pattern targeting 100 µm
height after reflow (screen printing, dispensing solder paste or by wire soldering).
Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible
using a vacuum nozzle and organic tip.
Temporary place the capacitor on land pattern assuming the solder paste (Flux)
will stick and maintain the capacitor.
Reflow the assembly module with a dedicated thermal profile (see reflow
recommendation profile).
Reproduction in whole or in part is prohibited without the
prior written consent of the copyright owner. The information
presented in this document does not form part of any
quotation or contract, is believed to be accurate and reliable
and may be changed without notice. No liability will be
accepted by the publisher for any consequence of its use.
Publication thereof does not convey nor imply any license
under patent- or other industrial or intellectual property rights.
For more information, please visit:
http://www.ipdia.com
To contact us, email to:
sales@ipdia.com
Date of release: 20
th
April 2012
Document identifier: