For Communications Equipment
MN195902
Digital Signal Processor for Image CODEC
Overview
The MN195902 is a high-speed, programmable digital
signal processor based on a vector pipeline architecture
for image processing applications. It incorporates many
features that make it ideal for highly efficient coding and
decoding of still and moving pictures in applications
involving the transmission, storage, and retrieval of
images.
Features
Flexible support for complex processing by simply
rewriting the contents of its internal program memory
Built-in dedicated hardware effective for image
CODEC, including
• Discrete cosine transform (DCT) converter
• Two-dimensional address generator
Architecture that links internal memory, a general-
purpose arithmetic unit, dedicated arithmetic unit, and
other components with a pipeline to better support
vector calculations, multiply-and-accumulate, and
other key image processing operations
ITU-T H.261 coding for the QCIF size (176
×
144)
with a decoding rate of 15 frames per second or higher
Applications
Image-based communications:
Moving picture videophones, video
conferencing systems, cable television
systems, image LANs, remote monitoring
systems, etc.
Image storage and retrieval:
Electronic still cameras, optical disc files,
image databases, etc.
Multimedia computers
MN195902
Pin Assignment
For Communications Equipment
D2[9]
D2[8]
V
DD3
V
SS3
D2[7]
D2[6]
D2[5]
D2[4]
D2[3]
D2[2]
D2[1]
D2[0]
V
DD2
V
SS2
D1[15]
D1[14]
D1[13]
D1[12]
D1[11]
D1[10]
D1[9]
D1[8]
D1[7]
D1[6]
V
DD1
V
SS1
D1[5]
D1[4]
D1[3]
D1[2]
D1[1]
D1[0]
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XSIEMP
SIRCLK
S1
XSOBSY
SOWCLK
S0
V
DD5
V
SS5
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
P0[7]
P0[6]
P0[5]
P0[4]
P0[3]
P0[2]
P0[1]
P0[0]
V
DD4
V
SS4
D2[15]
D2[14]
D2[13]
D2[12]
D2[11]
D2[10]
97
98
99
100
101
102
103
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
SPCLK
TEST0
TEST1
DRMODE0
DRMODE1
V
SS6
V
DD6
XWCS
XSRE
ST1
ST2
XHLD/RUN
XRST
XCS
XSWE
DRMODE2
V
SS7
SCLK
V
DD7
X801
X802
XRESEN1
XRESEN2
XOE1
XOE2
XWE1
XWE2
TEST2
TEST3
V
DDH
XCAS1
XCAS2
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
XRAS1
XRAS2
V
SS8
V
DD8
A1[0]
A1[1]
A1[2]
A1[3]
A1[4]
A1[5]
A1[6]
A1[7]
A1[8]
A1[9]
V
SS9
V
DD9
A1[10]
A1[11]
A2[0]
A2[1]
A2[2]
A2[3]
A2[4]
A2[5]
A2[6]
A2[7]
A2[8]
A2[9]
V
SS10
V
DD10
A2[10]
A2[11]
LQFP128-P-1818
For Communications Equipment
Vector Pipeline Processing Examples
MN195902
P instruction
SAG
Internal
memory
Internal
memory
Internal
memory
SAG
SAG
QP instruction
SAG
Internal
memory
SFT
REG
SFT
REG
SFT
REG
SFT
REG
Pipeline arithmetic unit
Pipeline arithmetic unit
REG
SFT
REG
ADD
Internal
memory
SAG
REG
SFT
Internal
memory
SAG
Q instruction
SAG
SAG
Internal
memory
Internal
memory
SFT
REG
SFT
REG
Pipeline arithmetic unit
REG
ADD
REG
MN195902
Block Diagram
For Communications Equipment
D1
A1
D2
SAG
SAG
SAG
SAG
A2
DRAM IF
SAG
BM1
1Kwd
BM2
1Kwd
DM
1Kwd
EALU
MPY
CTL
Program
CTL
IRAM
2Kwd
FREG
16wd
REG
DCT
FLT
SIO
SIO
PIO
PIO
ACC
REG
SAG
BM1
BM2
DM
IRAM, IROM
FREG0 to 15
EALU
Two-dimensional address generator
Internal memory (1024
×
16 bits)
Instruction memory (2048
×
16 bits)
Instruction memory (2048
×
16 bits)
Instruction memory (2048
×
32 bits)
General-purpose registers
Arithmetic unit
MPY
ACC
DCT
FLT
SIO
PIO
Multiplier
Accumulator
Discrete cosine transform converter
Filter
Serial interface
Parallel interface
For Communications Equipment
Pin Descriptions
Pin No.
15 to 24,
27 to 32
47 to 48,
51 to 60
71
73
77
64
66
75
123 to 128,
1, 2, 5 to 12
33, 34,
37 to 46
70
72
76
63
65
74
79
96
85
83
82
88
84
87
86
102
101
100
99
98
97
105 to 112
113 to 120
81, 92, 93
XWE2
XOE2
XBO2
XRAS2
XCAS2
XRFSEN2
SCLK
SPCLK
XHLD/RUN
XCS
XSWE
XSRE
XRST
ST1
ST2
SO
SOWCLK
XSOBSY
SI
SIRCLK
XSIEMP
PO (7:0)
PI (7:0)
DRMODE(2:0)
V
dd
V
ddh
V
ss
O/Z
O/Z
O
O/Z
O/Z
I
I
I
I
I
I
I
I
O
O
O/Z
O/Z
I
I
O/Z
I
O
I
I
I
I
I
External memory write control output (negative logic)
External memory read control output (negative logic)
A2 (11:0)
O/Z
XWE1
XOE1
XBO1
XRAS1
XCAS1
XRFSEN1
D2 (15:0)
O/Z
O/Z
O
O/Z
O/Z
I
I/O/Z
External memory write control output (negative logic)
External memory read control output (negative logic)
A1 (11:0)
I/O/Z
Symbol
D1 (15:0)
I/O
I/O/Z
MN195902
Function Description
Data bus for data transfers to and from external memory (EM1)
Address bus for data transfers to and from external memory (EM1)
External memory cycle bus occupation control output (negative logic)
External memory row address strobe output (negative logic)
External memory row address strobe output (negative logic)
External memory refresh enable signal (negative logic)
Data bus for data transfers to and from external memory (EM2)
Address bus for data transfers to and from external memory (EM2)
External memory cycle bus occupation control output (negative logic)
External memory row address strobe output (negative logic)
External memory row address strobe output (negative logic)
External memory refresh enable signal (negative logic)
System clock input
Serial port clock input
Operational mode transition control input
Chip select input (negative logic)
Internal memory write enable input for Hold/Slave mode (negative input)
Internal memory read enable input for Hold/Slave mode (negative input)
Reset input (negative input)
Operating status output
Operating status output
Serial out port data
Serial out port external write enable output
Serial out port external busy input (negative logic)
Serial in port data
Serial in port external read enable output
Serial in port external external empty input (negative logic)
Parallel out port data bus (PO7 is MSB)
Parallel in port data bus (PI7 is MSB)
External DRAM mode control inputs
Power supply pin
Power supply pin
Power supply pin
3.3[V]
5.0 to V
dd
[V]
0 [V]
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