CCD Delay Line Series
MN3880S
NTSC CCD Video Signal Delay Element
Overview
The MN3880S is a CCD signal delay element for video
signal processing applications.
It contains such components as a shift register clock
driver, charge I/O blocks, two CCD delay elements, a
clamp bias circuit, resampling output amplifiers, and
booster circuits.
The MN3880S samples the input using the supplied
clock signal with a frequency of 7.15909 MHz, twice the
NTSC color signal subcarrier frequency, and after add-
ing in the attached filter delay, produces independent de-
lays of 1 H (the horizontal scan period) each for the two
lines.
Pin Assignment
VBIASC
VOC
N.C.
V
DD
–V
BB
N.C.
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
VINC
N.C.
N.C.
X1
V
SS
N.C.
N.C.
VINY
Features
Single 4.9 V power supply
Single chip combining luminance signal delay
element and delay element for chrominance signal
after passing through a low pass filter
VOY
VBIASY
(TOP VIEW)
SOP016-P-0225
Applications
VCRs
1
MN3880S
Application Circuit Example
10µF
–
+
CCD Delay Line Series
VBIASC
(0.01µF)
12 V
SS
0.1µF
4 V
DD
Bias circuit
VINC 16
(0.01µF)
Charge input
block
CCD 454 stages
Charge
detection block
Resampling
output amplifier
2 VOC
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Timing adjustment
XI 13
1000pF
Waveform amplitude
adjustment block
Timing adjustment
øS driver
ø1 driver
ø2 driver
øR driver
øSH driver
øSH driver
Clamp circuit
VINY 9
– +
0.47µF
Charge input
block
–V
BB
5
1
CCD 454 stages
Charge
detection block
Resampling
output amplifier
8
7
VOY
(0.01µF)
VBIASY
(0.01µF)
Note: If the external capacitor attached to pin 5 is an electrolytic capacitor, attach the negative pole to pin 5.
4
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