For Communications Equipment
MN6155
PLL LSI with Built-In Prescaler
Overview
The MN6155 is a CMOS LSI for a phase-locked loop
(PLL) frequency synthesizer with serial data parameter
input.
It consists of a two-coefficient prescaler, variable
frequency divider, phase comparator, and charge pump.
It offers high-speed operation on a low power supply
voltage (1.0 to 1.4 V) and low power consumption (1.65
mW for V
DD
=1.1 V, F
IN
= R
IN
=90 MHz).
Other features include intermittent operation by the
power save (PS) control signal and high-speed pull-in that
rapidly corrects the phase differences occurring at the start
of operation.
It also offers two choices for the reference signal: self-
excited operation using the built-in inverter amplifier or
use of an external, separately excited oscillator.
Pin Assignment
X
IN
X
OUT
FV
V
DD
D
OP
V
SS
V
CP
F
IN
1
2
3
4
5
6
7
8
16
15
14
13
12
11
10
9
R
IN
RSL
LC
FR
PS
LE
DATA
CLK
(TOP VIEW)
SSOP016-P-0225
Features
Low power supply voltage: V
DD
=1.0 to 1.4V
Low power consumption: 1.65mW(V
DD
=1.10V,
F
IN
=90MHz, R
IN
=90MHz)
High-speed operation: F
IN
=90MHz, R
IN
=90MHz
(V
DD
=1.1V)
Frequency dividing ratios in reference frequency
dividing stage
6 to 131,070 for RSL at "H" level
(even number setting is available)
272 to 131,071 for RSL at "L" level
Frequency dividing ratios for comparator stage: 272
to 262,143
Power supply pin for built-in charge pump
V
CP
=2.5 to 3.2V
Output monitor pins for both comparator and reference
frequency dividing stages
MN6155
Block Diagram
RSL
4
6
13
FR
Swallow
counter
Switching
circuit
13-bit programmable counter
Phase
adjustment
15
V
DD
V
SS
R
IN
16
Prescaler and
phase adjustment
X
IN
3-bit counter
1
Prescaler
X
OUT
17-bit latch
2
7
5
CLK
Data control
18-bit shift register
9
V
CP
D
OP
Phase comparator
DATA
18-bit latch
10
LE
11
PS
12
Control
14
LC
3
For Communications Equipment
F
IN
8
Prescaler and
phase adjustment
Swallow
counter
14-bit programmable counter
FV
For Communications Equipment
Pin Descriptions
Pin No.
1
2
Symbol
X
IN
X
OUT
Function Description
Crystal oscillator connection pins:
X
IN
=Oscillator circuit input pin;
MN6155
(X
IN
is attached to a pull-up resistor when the PS or RSL pin is at "L" level.)
X
OUT
=Oscillator circuit output pin.
3
4
5
6
7
8
9
10
FV
V
DD
D
OP
V
SS
V
CP
F
IN
CLK
DATA
Frequency divider output signal in comparator stage.
Phase comparator input monitor.
Power supply
Low-pass filter connection pin. Use a passive filter.
Ground
Power supply pin for built-in charge pump
Frequency divider input pin in comparator stage.
Shift register clock input pin.
The chip latches data at the rising edge of the CLK signal.
Shift register data input pin.
The final two bits in the data select the write latch:
"11" for R-latch; "01" for N-latch.
11
12
LE
PS
Load enable signal input pin.
This is the latch-write-enable signal. It is at "H" level for write.
Power save control signal input pin.
"H" level input starts the frequency divider and places the chip in operational
mode. "L" level input places the chip in standby mode, which saves power.
The chip switches the internal charge pump output to the H-z state and the loop
is opened.
13
14
FR
LC
Reference frequency divider output signal.
Phase comparator input monitor.
Charge pump control signal output pin.
When frequency divider operation is stopped, this pin is at "L" level, the
internal charge pump output is in the high-impedance state, and the loop is opened.
15
RSL
Reference signal selection pin.
"H" level selects self-excited oscillator (X
IN
and X
OUT
).
"L" level selects external oscillator (R
IN
).
16
R
IN
External reference oscillation input pin.
This pin is attached to a pull-up resistor when the PS pin is at "L" level or the
RSL pin is at "H" level.
MN6155
MN6155 Frequency Dividing Data Settings
1)
Comparator side frequency dividing data
FV = F
IN
÷ {(16
×
N) + A}
For Communications Equipment
2)
Reference side frequency dividing data
a) Low-speed operation (RSL pin at "H" level, using X
IN
)
FR = X
IN
÷ R
b) High-speed operation (RSL pin at "L" level, using R
IN
)
FR =R
IN
÷ {(16
×
NR) + AR}
where
F
IN
: Comparator side frequency
R
IN
: High-speed reference frequency
X
IN
: Low-speed reference oscillator frequency
FV
: Comparator frequency divider stage output frequency
FR
: Reference frequency divider stage output frequency
N
: Setting for 14-bit programmable counter on comparator side
A
: Setting for 4-bit swallow counter on comparator side
R
: Setting for 17-bit programmable counter on low-speed reference side
NR
: Setting for 13-bit programmable counter on high-speed reference side
AR
: Setting for 4-bit swallow counter on low-speed reference side
(Note that N should be greater than A; NR, greater than AR.)
N-Side Latch Data
MSB
14 bits
Programmable
counter setting (N)
4 bits
Swallow counter
setting (A)
LSB
R-Side Latch Data
Low-speed operation
MSB
17 bits
Programmable counter
setting (N)
LSB
High-speed operation
MSB
13 bits
Programmable counter
setting (NR)
4 bits
Swallow counter
setting (AR)
LSB
For Communications Equipment
Note on Setting Frequency Dividing Data Input
1) Frequency dividing data input
(1) Reference side
Data input direction
MSB
17-bit frequency dividing data
LSB
1 bit
1 bit
Control bits
MN6155
"L"
Frequencey
Write selection
dividing stage
"H" level
selection "H" level
1
CLK
2
17
18
19
DATA
MSB
LE
LSB
(2) Comparating side
Data input direction
*1
3-bit test data
3 bits "L" level
18-bit frequency dividing data
1 bit
1 bit
"L"
Control bits
1
CLK
2
3
4
5
Frequencey
Write selection
dividing stage
"H" level
selection "L" level
21
22
23
DATA
MSB
LE
Notes
LSB
1.*1:
Preceding the input of the frequency dividing data for the comparating side, input test pattern consisting
of three "L" level bits to produce normal operation. Never use any other pattern.
2.
When the power is first applied, internal operation remains in an unstable state until data is written. To
eliminate the risk of excessive current consumption, keep the PS pin at "L" level.
3.
When the power is first applied, the data settings are indeterminate. Always write data to the chip before
4.
starting operation.
Enter the data to fill the entire latch:
Reference side: 19 bits (17 bits for the frequency divider setting and 2 for control bits)
Comparating side: 23 bits (3 bits for the test pattern, 18 bits for the frequency divider setting, and 2 for
control bits)
Drive the LE pin at "L" level while writing the data.
"H" level input from the LE pin causes the chip to read the data only when the CLK pin and the DATA pin
are both at "L" level.
Writes are possible when the PS pin is either "H" or "L" level.
Input the data MSB first.
The data are inputted at the rising edge of the CLK signal.
5.
6.
7.
8.
9.
单片机
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